Memory device for repairing a neighborhood of rows in a memory array using a patch table

• US 7,958,390 B2
• Filed: 05/15/2007
• Issued: 06/07/2011
• Est. Priority Date: 05/15/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Moore, Christopher S., Bosch, Derek J.
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): Truong; Loan
• Application Number:
  US11/803,756
• Publication Number:
  US 20080285365A1
• Time in Patent Office: 1,484 Days
• Field of Search: 714/8, 714/6.1, 714/6.11, 714/6.13, 714/6.32, 365/200, 711/153
• US Class Current: 714/6.13
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N−1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N−1, N, and N+1 to a table stored in the memory device.

Claims

1. A memory device comprising:

a memory array;

a temporary storage area; and

circuitry operative to;

store, in the temporary storage area;

(i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N−

1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array;

write the first data in row N in the memory array; and

in response to an error in writing the first data in row N in the memory array;

write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device; and

add addresses of rows N−

1, N, and N+1 to a table stored in the memory device, wherein the table indicates which rows in the repair area should be used instead of rows N−

1, N, and N+1;

wherein the circuitry is operative to write the first data, the second data, if any, and the third data, if any, in respective rows in the repair area such that there are intervening blank rows between the respective rows.

2. The memory device of claim 1, wherein the circuitry operative to add the addresses of rows N−

1, N, and N+1 to the table such that there are intervening blank rows between the addresses in the table.

3. The memory device of claim 1, wherein the circuitry is further operative to:

receive a command to perform one of a read or a write operation to an address of one of rows N−

1, N, and N+1;

compare the address to addresses listed in the table; and

determine which address in the repair area should be used for said one of a read or a write operation instead of the address of said one of rows N−

1, N, and N+1.

4. The memory device of claim 1, wherein third data is not stored in row N+1 in the memory array, and wherein the circuitry is further operative to:

store, in the temporary storage area of the memory device, third data to be stored in row N+1 in the memory array; and

in response to the error in writing the first data in row N in the memory array, write the third data in a row in the repair area in the memory device.

5. The memory device of claim 1, wherein a row stores two pages of data, wherein the first data comprises a first page of data, wherein row N stores a second page of data, and wherein the circuitry is further operative to:

store, in the temporary storage area, the second page of data; and

in response to the error in writing the first data in row N in the memory array, write the second page of data in a same repair row in the repair area as the first data.

6. The memory device of claim 1 further comprising a controller in communication with the memory array, wherein the temporary storage area and the circuitry are part of the controller.

7. The memory device of claim 1, wherein the memory array comprises a three-dimensional memory array comprising a plurality of memory cell layers stacked vertically above one another above a single silicon substrate.

8. A memory device comprising:

a memory array;

a temporary storage area; and

circuitry operative to;

receive an address of row N in the memory array;

determine whether the address of row N is present in a table stored in the memory device;

if the address of row N is present in the table, remap the address to an address in a repair area of the memory device;

if the address of row N is not present in the table;

store, in the temporary storage area;

(i) first data to be stored in row N in the memory array (ii) second data, if any, stored in row N−

1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array;

write the first data in row N in the memory array; and

in response to an error in writing the first data in row N in the memory array;

write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device; and

add addresses of rows N−

1, N, and N+1 to the table, wherein the table indicates which rows in the repair area should be used instead of rows N−

1, N, and N+1;

wherein the circuitry is operative to write the first data, the second data, if any, and the third data, if any, in respective rows in the repair area such that there are intervening blank rows between the respective rows.

9. The memory device of claim 8, wherein the circuitry is operative to add the addresses of rows N−

1, N, and N+1 to the table such that there are intervening blank rows between the addresses in the table.

10. The memory device of claim 8, wherein the circuitry is further operative to remap the address of the repair area to a new address in the repair area if the address of the repair area is also present in the table.

11. The memory device of claim 8, wherein the circuitry is further operative to add an address of the row of the repair area to the table and write the data of the row to another row in the repair area if there is an error in writing the data of the row to the repair area.

12. The memory device of claim 8, wherein the circuitry is further operative to:

receive a command to perform one of a read or a write operation to an address of one of rows N−

1, N, and N+1;

compare the address to addresses listed in the table; and

determine which address in the repair area should be used for said one of a read or a write operation instead of the address of said one of rows N−

1, N, and N+1.

13. The memory device of claim 8, wherein third data is not stored in row N+1 in the memory array, and wherein the circuitry is further operative to:

store, in the temporary storage area of the memory device, third data to be stored in row N+1 in the memory array; and

in response to the error in writing the first data in row N in the memory array, write the third data in a row in the repair area in the memory device.

14. The memory device of claim 9, wherein a row stores two pages of data, wherein the first data comprises a first page of data, wherein row N stores a second page of data, and wherein the circuitry is further operative to:

store, in the temporary storage area, the second page of data; and

in response to the error in writing the first data in row N in the memory array, write the second page of data in a same repair row in the repair area as the first data.

15. The memory device of claim 8 further comprising a controller in communication with the memory array, wherein the temporary storage area and the circuitry are part of the controller.

16. The memory device of claim 8, wherein the memory array comprises a three-dimensional memory array comprising a plurality of memory cell layers stacked vertically above one another above a single silicon substrate.