System and method for on-board timing margin testing of memory modules

• US 7,958,412 B2
• Filed: 02/24/2010
• Issued: 06/07/2011
• Est. Priority Date: 09/12/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US12/711,982
• Publication Number:
  US 20100153794A1
• Time in Patent Office: 468 Days
• Field of Search: 714/718, 714/719, 714/742, 365/201
• US Class Current: 714/718
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.

Claims

1. A memory hub for accessing a plurality of memory devices, the memory huh comprising:

a switch;

a link interface coupled to the switch for receiving memory requests for access to at least one of the memory devices;

a memory device interface coupled to the switch and the memory devices; and

a self-test module coupled to at least one of the memory devices via the switch, wherein the self-test module is operable to couple a series of corresponding first and second signals to the at least one memory device and to alter the relative timing between when some of the corresponding first and second signals in the series are coupled to the at least one memory device over a range, the self-test module further receiving output signals from the at least one memory device and determining based on the received output signals whether the at least one memory device properly responded to the series of first and second signals.