Flash memory device and method

• US 7,958,430 B1
• Filed: 06/19/2006
• Issued: 06/07/2011
• Est. Priority Date: 06/20/2005
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kolokowsky, Steve H., McCoy, Mark D.
• Primary Examiner(s): Baderman, Scott T
• Assistant Examiner(s): Ahmed, Enam
• Application Number:
  US11/425,004
• Time in Patent Office: 1,814 Days
• Field of Search: 714/763
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

An improved flash memory device and method for improving the performance and reliability of a flash memory device is provided. According to one embodiment, a method for writing data to a memory device may include writing the data to a temporary storage location within the memory device before the data is copied to another location within the memory device, incrementing a count value to indicate that the data has been copied, and repeating the step of writing, if the count value is less than a threshold value. If the count value is greater than or equal to the threshold value, the method may write the data to an external memory controller, where the data is checked for errors and corrected if an error is found, before the data is copied to the other location within the memory device.

Claims

1. A memory device comprising:

data storage locations;

a controller configured to copy a data set from a selected data storage location within the memory device;

a counter configured to count a number of times the data set is copied from the selected data storage location;

the controller also configured to copy the data set to an individual data storage location within the memory device;

(a) without error checking when the count does not exceed a threshold value, and

(b) when the count exceeds the threshold value, after error checking and correction has been performed on the copy of the data set.

2. The memory device as recited in claim 1, further comprising an external memory controller configured to perform said error checking and correction and to copy the corrected data to the individual data storage location within the memory device.

3. The memory device as recited in claim 2, wherein a first monolithic substrate embodies the memory device, and a second monolithic substrate embodies the external memory controller.

4. The memory device as recited in claim 1, wherein said counter is incremented each time the data set of a particular page within a particular block is being written to.

5. The memory device as recited in claim 1, wherein the counter is incremented each time the data set is copied for a particular page within a particular block.

6. The memory device as recited in claim 1, wherein the counter is reset each time the count is equal to the threshold value.

7. The memory device as recited in claim 1, wherein the threshold value is set at approximately the number of times a storage location within the memory device can reliably store said data set.

8. The memory device as recited in claim 1, wherein the controller is configured to initiate the error checking and correction during times when a copy operation is not pending and before the count is greater than the threshold value.

9. A method for copying data in a memory device, the method comprising:

in response to a copy command to copy data from a data location in the memory device, copying the data to a data buffer within the memory device, checking a copy count value, and incrementing the copy count value to indicate that the data has been copied from the data location to the data buffer;

when the copy count value does not exceed a threshold value, copying the data from the data buffer to an individual data location within the memory device without error checking; and

when the copy count value exceeds the threshold value, before copying the data to the individual data location within the memory device, checking the data for errors and correcting when an error is found.

10. The method as recited in claim 9, wherein the data is checked for errors by writing the data from the data buffer to a memory controller embodied upon a second monolithic substrate external to and separate from a first monolithic substrate upon which the memory device is embodied.

11. The method as recited in claim 9, wherein when the copy count value exceeds the threshold value, the method further comprises resetting the copy count value once the data has been checked for errors.

12. The method as recited in claim 9, further comprising periodically performing the error checking and correction during times when a copy operation is not pending.

13. A memory system, comprising:

a memory device coupled to a memory controller external to the memory device;

the memory device includes;

an array of non-volatile storage cells;

a data buffer configured to receive a set of data copied from a first location within the array of storage cells;

a counter configured to provide a copy count of a number of times the set of data is copied from the first location; and

a control unit configured to (a) forward the set of data from the data buffer to an individual location in the array of storage cells without error checking when the copy count does not exceed a threshold value equal to at least one, and (b) route the set of data from the data buffer to the memory controller when the copy count exceeds the threshold value;

the memory controller includes;

an error checking and correction unit configured to check for and to correct errors in the set of data routed to the memory controller and to copy the corrected set of data to the memory device data buffer for copying to the individual location in the array of storage cells.

14. The memory system as recited in claim 13, wherein the error checking and correction unit comprises combinatorial logic that combines the set of data with error correction data to produce a result that indicates whether the set of data contains an error.

15. The memory system as recited in claim 13, wherein the checking and error correction unit comprises combinatorial logic that combines the set of data with error correction data to produce a result that indicates which bit of the error correction data is erroneous, and a proper bit value for the erroneous bit.

16. The memory system as recited in claim 13, wherein the checking and error correction unit comprises combinatorial logic configured to combine the set of data with error correction data to produce a result that indicates which bit of the set of data is erroneous, and configured to correct the erroneous bit before the set of data is copied to the individual location in the array of storage cells.

17. The memory system as recited in claim 16, wherein the counter is cleared after the set of data is checked for errors.

18. The memory system as recited in claim 13, wherein at least a portion of the memory device is periodically checked for errors when read, write or copy commands are not being sent to the storage cells or the memory controller.