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Method and computer program for configuring an integrated circuit design for static timing analysis

  • US 7,958,473 B2
  • Filed: 05/09/2008
  • Issued: 06/07/2011
  • Est. Priority Date: 02/27/2006
  • Status: Active Grant
First Claim
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1. A processor-based method for conducting a static timing analysis of an integrated circuit design, the method comprising the steps of:

  • receiving with the processor an integrated circuit design defined by modules and submodules,producing and displaying with the processor a hierarchical representation of the modules and submodules of the integrated circuit design,for each submodule in the hierarchical representation, and using an interface connected to the processor, indicating a desired one only of a selection of representations of the submodule, where the representations comprise,(a) a black box approximation comprising input and output parameters for the submodule but no cell and interconnect information for the submodule,(b) a timing model comprising timing at boundaries of the submodule but no cell and interconnect information for the submodule, and(c) a netlist comprising cell and interconnect information for the submodule,generating with the processor a static timing analysis scenario file, where for each submodule the static timing analysis scenario file includes only the selected representation of the submodule, andperforming the static timing analysis using the static timing analysis scenario file as input.

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