Method and computer program for configuring an integrated circuit design for static timing analysis
First Claim
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1. A processor-based method for conducting a static timing analysis of an integrated circuit design, the method comprising the steps of:
- receiving with the processor an integrated circuit design defined by modules and submodules,producing and displaying with the processor a hierarchical representation of the modules and submodules of the integrated circuit design,for each submodule in the hierarchical representation, and using an interface connected to the processor, indicating a desired one only of a selection of representations of the submodule, where the representations comprise,(a) a black box approximation comprising input and output parameters for the submodule but no cell and interconnect information for the submodule,(b) a timing model comprising timing at boundaries of the submodule but no cell and interconnect information for the submodule, and(c) a netlist comprising cell and interconnect information for the submodule,generating with the processor a static timing analysis scenario file, where for each submodule the static timing analysis scenario file includes only the selected representation of the submodule, andperforming the static timing analysis using the static timing analysis scenario file as input.
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Abstract
A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.
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Citations
12 Claims
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1. A processor-based method for conducting a static timing analysis of an integrated circuit design, the method comprising the steps of:
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receiving with the processor an integrated circuit design defined by modules and submodules, producing and displaying with the processor a hierarchical representation of the modules and submodules of the integrated circuit design, for each submodule in the hierarchical representation, and using an interface connected to the processor, indicating a desired one only of a selection of representations of the submodule, where the representations comprise, (a) a black box approximation comprising input and output parameters for the submodule but no cell and interconnect information for the submodule, (b) a timing model comprising timing at boundaries of the submodule but no cell and interconnect information for the submodule, and (c) a netlist comprising cell and interconnect information for the submodule, generating with the processor a static timing analysis scenario file, where for each submodule the static timing analysis scenario file includes only the selected representation of the submodule, and performing the static timing analysis using the static timing analysis scenario file as input. - View Dependent Claims (2, 3, 4)
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5. A non-transitory computer readable storage medium tangibly embodying instructions for a processor that when executed by the processor implement a method comprising steps of:
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receiving with the processor an integrated circuit design defined by modules and submodules, producing and displaying with the processor a hierarchical representation of the modules and submodules of the integrated circuit design, for each submodule in the hierarchical representation, and using an interface connected to the processor, indicating a desired one only of a selection of representations of the submodule, where the representations comprise, (a) a black box approximation comprising input and output parameters for the submodule but no cell and interconnect information for the submodule, (b) a timing model comprising timing at boundaries of the submodule but no cell and interconnect information for the submodule, and (c) a netlist comprising cell and interconnect information for the submodule, generating with the processor a static timing analysis scenario file, where for each submodule the static timing analysis scenario file includes only the selected representation of the submodule, and performing the static timing analysis using the static timing analysis scenario file as input. - View Dependent Claims (6, 7, 8)
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9. A static timing analysis scenario file generator comprising:
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a processor for receiving an integrated circuit design that is defined by modules and submodules, the processor further for producing and displaying a hierarchical representation of the modules and submodules of the integrated circuit design, for each submodule in the hierarchical representation, and using an interface connected to the processor, indicating a desired one only of a selection of representations of the submodule, where the representations comprise, (a) a black box approximation comprising input and output parameters for the submodule but no cell and interconnect information for the submodule, (b) a timing model comprising timing at boundaries of the submodule but no cell and interconnect information for the submodule, and (c) a netlist comprising cell and interconnect information for the submodule, the processor further for generating the static timing analysis scenario file, where for each submodule the static timing analysis scenario file includes only the selected representation of the submodule, and performing the static timing analysis using the static timing analysis scenario file as input. - View Dependent Claims (10, 11, 12)
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Specification