Highly threaded static timer
First Claim
1. A method for executing a multithreaded algorithm to perform a static timing analysis of a chip, comprising:
- traversing the chip to identify a plurality of components within a logic circuit of the chip, each of the plurality of components including a plurality of nodes;
defining a waveform graph for the plurality of nodes;
generating a first and a second virtual graph from the waveform graph;
assigning the first virtual graph for running an early mode propagation;
assigning the second virtual graph for running a late mode propagation;
processing the plurality of nodes in the first and the second virtual graphs independently using a first and a second thread to compute arrival time domain dataset values at each of the plurality of nodes;
performing a timing check at end point nodes in each of the first and the second virtual graphs using the time domain dataset values to determine any timing violations within the chip circuit; and
processing the plurality of nodes in the first and the second virtual graphs independently using a third and a fourth thread to compute required time domain dataset values at each of the plurality of nodes,wherein operations are executed by a processor.
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Accused Products
Abstract
Various methods and apparatus for executing a multithreaded algorithm that performs a static timing analysis of an integrated circuit chip (chip) include logic for traversing the chip to identify a plurality of components (cells or nodes) within a chip circuit of the chip. A waveform graph is defined for the identified nodes. One or more virtual graphs are generated from the waveform graph. The plurality of nodes in the one or more virtual graphs are processed using multiple threads to obtain quadruplet of time domain dataset values representing the different modes of propagation for each node. A timing check is performed at an end node of the virtual graphs using the quadruplet of time domain dataset values to determine any timing violation within the chip design.
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Citations
26 Claims
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1. A method for executing a multithreaded algorithm to perform a static timing analysis of a chip, comprising:
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traversing the chip to identify a plurality of components within a logic circuit of the chip, each of the plurality of components including a plurality of nodes; defining a waveform graph for the plurality of nodes; generating a first and a second virtual graph from the waveform graph; assigning the first virtual graph for running an early mode propagation; assigning the second virtual graph for running a late mode propagation; processing the plurality of nodes in the first and the second virtual graphs independently using a first and a second thread to compute arrival time domain dataset values at each of the plurality of nodes; performing a timing check at end point nodes in each of the first and the second virtual graphs using the time domain dataset values to determine any timing violations within the chip circuit; and processing the plurality of nodes in the first and the second virtual graphs independently using a third and a fourth thread to compute required time domain dataset values at each of the plurality of nodes, wherein operations are executed by a processor. - View Dependent Claims (2, 3)
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4. A method for executing a multithreaded algorithm to perform a static timing analysis of a chip, comprising:
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traversing the chip to identify a plurality of components within a logic circuit of the chip, each of the plurality of components including a plurality of nodes; defining a waveform graph for the plurality of nodes; generating a first and a second virtual graph from the waveform graph; assigning the first virtual graph for running an early mode propagation; assigning the second virtual graph for running a late mode propagation; processing the plurality of nodes in the first and the second virtual graphs independently using a plurality of threads to compute time domain dataset values at each of the plurality of nodes; and performing a timing check at end nodes in each of the first and the second virtual graphs using the time domain dataset values to determine any timing violations within the chip circuit, wherein operations are executed by a processor. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for executing a multithreaded algorithm to perform a static timing analysis of a chip, comprising:
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traversing the chip to identify a plurality of components with in a chip circuit of the chip, each of the plurality of components including a plurality of nodes; defining a waveform graph for the plurality of nodes; generating a virtual graph identifying one or more domains in the waveform graph, each of the domains representing a unique transmission path from a clock header node through plurality of nodes associated with the clock header node of the waveform graph; processing the plurality of nodes in each of the domains in the virtual graph using multiple threads to obtain time domain dataset values at each node, each thread assigned to process the plurality of nodes in each domain; and performing a timing check to determine any timing violation within the chip circuit, wherein operations are executed by a processor. - View Dependent Claims (18, 19, 20, 21)
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22. A method for executing a multithreaded algorithm to perform a static timing analysis of a chip, comprising:
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traversing the chip to identify a plurality of components with in a chip circuit of the chip, each of the plurality of components including a plurality of nodes; defining a waveform graph for the plurality of nodes; generating a first and second virtual graphs from the waveform graph; defining one or more domains within each of the first and second virtual graphs, each of the domains representing a signal transmission path through plurality of nodes associated with a single header node at the first and second virtual graphs; assigning the first virtual graph for running an early mode propagation; assigning the second virtual graph for running a late mode propagation; processing the plurality of nodes in each of the domains in the first and the second virtual graphs independently using a plurality of threads to obtain time domain dataset values at each of the plurality of nodes, each of the plurality of threads assigned to process a domain; and performing a timing check at the first and second virtual graphs to determine any timing violations within the chip circuit, wherein operations are executed by a processor. - View Dependent Claims (23, 24, 25, 26)
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Specification