Method for fabrication of a semiconductor device and structure

• US 7,960,242 B2
• Filed: 07/30/2010
• Issued: 06/14/2011
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Beinglass, Israel, Cronquist, Brian, Sekar, Deepak C., Or-Bach, Zvi, de Jong, Jan Lodewijk
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Nikmanesh; Seahvosh J
• Application Number:
  US12/847,911
• Publication Number:
  US 20100291749A1
• Time in Patent Office: 319 Days
• Field of Search: 438/401, 438/197, 257/E21.023, 257/E21.598
• US Class Current: 438/401
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5252 : comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H03K 17/687 : the devices being field-effect transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/17704 : the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17756 : for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17764 : for reliability
• CPC Class Codes: H03K 19/17796 : for physical disposition of blocks
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/25 : One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

Claims

1. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks;

transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and

performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

2. The method according to claim 1 wherein:

said monocrystalline layer further comprises transistors formed therein.

3. The method according to claim 1 wherein said transferring comprises:

performing layer transfer of said monocrystalline layer to a carrier; and

performing layer transfer of said monocrystalline layer on top of said metal layers from said carrier.

4. The method according to claim 1, further comprising:

etching said monocrystalline layer to form a plurality of planar transistors.

5. The method according to claim 1, further comprising:

etching said monocrystalline layer to form a plurality of p-type and n-type transistors.

6. The method according to claim 1, further comprising:

optical annealing of at least one region of said monocrystalline layer.

7. The method according to claim 1, wherein:

said monocrystalline layer comprises a repeating pattern.

8. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks;

preparing a monocrystalline layer comprising semiconductor regions comprising partially-formed transistors, and second alignment marks;

performing layer transfer of said monocrystalline layer on top of said metal layers; and

finalizing forming said transistors after said layer transfer.

9. The method according to claim 8 further comprises:

performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

10. The method according to claim 8, wherein said transfer comprises:

performing layer transfer of said monocrystalline layer to a carrier; and

performing layer transfer of said monocrystalline layer on top of said metal layers from said carrier.

11. The method according to claim 8 wherein said transistors are planar transistors.

12. The method according to claim 8, further comprising:

optical annealing of at least one region of said monocrystalline layer.

13. The method according to claim 8, wherein

said transistors are of p-type or n-type transistors.

14. A method of manufacturing a semiconductor wafer, the method comprising:

providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks;

preparing a monocrystalline layer comprising semiconductor regions, and second alignment marks;

performing layer transfer of said monocrystalline layer, first to a carrier and then on top of said metal layers; and

etching said monocrystalline layer to define individual transistors.

15. The method according to claim 14, further comprising:

performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

16. The method according to claim 14, wherein said monocrystalline layer comprises partially formed transistors.

17. The method according to claim 14, wherein said monocrystalline layer comprises a repeating pattern.

18. The method according to claim 14, wherein said transistors are planar transistors.

19. The method according to claim 14, wherein said transistors comprise p-type transistors and n-type transistors.

20. The method according to claim 14, further comprising:

optical annealing of at least one region of said monocrystalline layer.