Method for forming a double embossing structure

• US 7,960,269 B2
• Filed: 07/24/2006
• Issued: 06/14/2011
• Est. Priority Date: 07/22/2005
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lo, Hsin-Jung, Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): Jones; Eric W
• Application Number:
  US11/491,117
• Publication Number:
  US 20070045855A1
• Time in Patent Office: 1,786 Days
• Field of Search: 438/598, 257/777, 257/778, 257/E21.004, 257/508, 257/E23.021, 257/E25.021, 257/173, 257/174
• US Class Current: 438/598
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/13021 : the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48844 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.

Claims

1. A method for fabricating a circuit component, comprising:

providing a silicon substrate, a transistor in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first circuit layer over said first dielectric layer, a second dielectric layer over said first circuit layer and over said first dielectric layer, a second circuit layer over said second dielectric layer, and a passivation layer over said first and second circuit layers and over said first and second dielectric layers, wherein said passivation layer comprises a nitride layer;

forming a first metal layer over said passivation layer;

forming a first photoresist layer on said first metal layer, wherein a first opening in said first photoresist layer exposes a first region of said first metal layer;

after said forming said first photoresist layer, forming a second metal layer over said first region;

after said forming said second metal layer, removing said first photoresist layer;

forming a second photoresist layer on said second metal layer, wherein a second opening in said second photoresist layer exposes a second region of said second metal layer;

after said forming said second photoresist layer, forming a third metal layer over said second region;

after said forming said third metal layer, removing said second photoresist layer;

after said removing said second photoresist layer and said removing said first photoresist layer, removing said first metal layer not under said second metal layer;

after said removing said first metal layer not under said second metal layer, forming a polymer layer on said second metal layer and on a top of said third metal layer;

removing said polymer layer on said top;

after said removing said polymer layer on said top, forming a fourth metal layer over said polymer layer and over said top;

after said forming said fourth metal layer, forming a third photoresist layer on said fourth metal layer, wherein a third opening in said third photoresist layer exposes a third region of said fourth metal layer;

after said forming said third photoresist layer, forming a fifth metal layer over said third region;

after said forming said fifth metal layer, removing said third photoresist layer;

after said forming said fifth metal layer, forming a fourth photoresist layer on said fifth metal layer, wherein a fourth opening in said fourth photoresist layer exposes a fourth region of said fifth metal layer;

after said forming said fourth photoresist layer, forming a sixth metal layer over said fourth region;

after said forming said sixth metal layer, removing said fourth photoresist layer; and

after said removing said fourth photoresist layer and said removing said third photoresist layer, removing said fourth metal layer not under said fifth metal layer.

2. The method of claim 1, wherein said forming said second metal layer comprises electroplating a copper layer with a thickness between 1 and 20 micrometers on said first region and in said first opening.

3. The method of claim 1, wherein said forming said fifth metal layer comprises electroplating a copper layer with a thickness between 1 and 20 micrometers on said third region and in said third opening.

4. The method of claim 1, wherein said removing said polymer on said top comprises polishing said polymer layer.

5. The method of claim 1, wherein said forming said third metal layer comprises electroplating a copper layer on said second region and in said second opening.

6. The method of claim 1, wherein said forming said sixth metal layer comprises electroplating a copper layer on said fourth region and in said fourth opening.

7. The method of claim 1, wherein said nitride layer has a thickness between 0.2 and 1.2 micrometers.

8. A method for fabricating a circuit component, comprising:

providing a silicon substrate, a transistor in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first circuit layer over said first dielectric layer, a second dielectric layer over said first circuit layer and over said first dielectric layer, a second circuit layer in a first opening in said second dielectric layer, and a passivation layer over said first and second circuit layers and over said first and second dielectric layers, wherein said second circuit layer comprises a barrier layer at a bottom and a sidewall of said first opening and a first copper layer on said barrier layer, wherein said first copper layer comprises electroplated copper, wherein said passivation layer comprises a nitride layer;

forming a first metal layer over said passivation layer;

forming a first photoresist layer on said first metal layer, wherein a second opening in said first photoresist layer exposes a first region of said first metal layer;

after said forming said first photoresist layer, forming a second metal layer over said first region;

after said forming said second metal layer, removing said first photoresist layer;

after said removing said first photoresist layer, removing said first metal layer not under said second meter layer;

after said removing said first metal layer not under said second metal layer, forming a first polymer layer on said second metal layer and over said passivation layer;

forming a third metal layer over said first polymer layer and over said second metal layer, wherein said third metal layer is connected to said second metal layer through a third opening in said first polymer layer;

forming a second photoresist layer on said third metal layer, wherein a fourth opening in said second photoresist layer exposes a second region of said third metal layer;

after said forming said second photoresist layer, forming a fourth metal layer over said second region;

after said forming said fourth metal layer, removing said second photoresist layer;

after said forming said fourth metal layer, forming a third photoresist layer on said fourth metal layer, wherein a fifth opening in said third photoresist layer exposes a third region of said fourth metal layer;

after said forming said third photoresist layer, forming a fifth metal layer over said third region;

after said forming said fifth metal layer, removing said third photoresist layer; and

after said removing said second photoresist layer and said removing said third photoresist layer, removing said third metal layer not under said fourth metal layer.

9. The method of claim 8, wherein said forming said second metal layer comprises electroplating a second copper layer with a thickness between 1 and 20 micrometers on said first region and in said second opening.

10. The method of claim 8, wherein said forming said first polymer layer comprises a spin coating process.

11. The method of claim 8 further comprising forming a second polymer layer on said passivation layer, followed by said forming said first metal layer further over said second polymer layer.

12. The method of claim 8, wherein said forming said fourth metal layer comprises electroplating a second copper layer on said second region and in said fourth opening.

13. The method of claim 8, wherein said nitride layer has a thickness between 0.2 and 1.2 micrometers.

14. A method for fabricating a circuit component, comprising:

forming a first metal layer over a substrate;

forming a first photoresist layer on said first metal layer, wherein a first opening in said first photoresist layer exposes a first region of said first metal layer;

after said forming said first photoresist layer, forming a second metal layer over said first region;

after said forming said second metal layer, removing said first photoresist layer;

after said removing said first photoresist layer, forming a polymer layer on said second metal layer and on said first metal layer, wherein a second opening in said polymer layer exposes a second region of said second metal layer; and

removing said first metal layer not under said polymer layer.

15. The method of claim 14, after said forming said polymer layer, further comprising:

forming a second photoresist layer on said first metal layer and on said polymer layer, wherein a third opening in said second photoresist layer exposes said second region;

after said forming said second photoresist layer, forming a third metal layer over said second region; and

after said forming said third metal layer, removing said second photoresist layer, followed by said removing said first metal layer not under said polymer layer.

16. The method of claim 15, wherein said forming said third metal layer comprises forming a gold layer over said second region and in said second opening.

17. The method of claim 15, wherein said forming said third metal layer comprises electroplating a tin-containing layer over said second region and in said second opening.

18. The method of claim 15, wherein said forming said third metal layer comprises electroplating a copper layer on said second region and in said second opening.

19. The method of claim 14, wherein said forming said second metal layer comprises electroplating a copper layer with a thickness between 1 and 20 micrometers on said first region and in said first opening.

20. The method of claim 14, wherein said forming said polymer layer comprises a spin coating process.

21. A method for fabricating a circuit component, comprising:

forming a first metal layer over a substrate;

forming a first photoresist layer on said first metal layer, wherein a first opening in said first photoresist layer exposes a first region of said first metal layer;

forming a second metal layer over said first region;

after said forming said second metal layer, removing said first photoresist layer;

after said removing said first photoresist layer, removing said first metal layer not under said second metal layer;

after said removing said first metal layer not under said second metal layer, forming a polymer layer over said second metal layer and over said substrate;

forming a third metal layer over said polymer layer and over said second metal layer, wherein said third metal layer is connected to said second metal layer through a second opening in said polymer layer;

forming a second photoresist layer on said third metal layer, wherein a third opening in said second photoresist layer exposes a second region of said third metal layer;

forming a fourth metal layer over said second region;

after said forming said fourth metal layer, removing said second photoresist layer;

forming a third photoresist layer on said fourth metal layer, wherein a fourth opening in said third photoresist layer exposes a third region of said fourth metal layer;

forming a fifth metal layer over said third region;

after said forming said fifth metal layer, removing said third photoresist layer; and

after said removing said third photoresist layer and said removing said second photoresist layer, removing said third metal layer not under said fourth metal layer.

22. The method of claim 21, wherein said forming said second metal layer comprises electroplating a copper layer with a thickness between 1 and 20 micrometers on said first region and in said first opening.

23. The method of claim 21, wherein said forming said fourth metal layer comprises electroplating a copper layer on said second region and in said third opening.