Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging

• US 7,960,272 B2
• Filed: 06/11/2007
• Issued: 06/14/2011
• Est. Priority Date: 10/24/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Shih-Hsiung, Lee, Jin-Yuan
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US11/761,360
• Publication Number:
  US 20070232053A1
• Time in Patent Office: 1,464 Days
• Field of Search: 438612-624, 438106-108, 257/522, 257737-738
• US Class Current: 438/613
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0233 Structure of the redistribution layers
• CPC Class Codes: H01L 2224/02335 Free-standing redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

Claims

1. A method for fabricating a circuit component, comprising:

providing a silicon substrate and a silicon-nitride layer over said silicon substrate;

forming a sacrificial layer over said silicon-nitride layer;

forming a first metal layer comprising a first portion over a top surface of said sacrificial layer and at a sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer;

forming a photoresist layer on said first metal layer, wherein an opening in said photoresist layer exposes said first and second portions of said first metal layer;

after said forming said photoresist layer, forming a second metal layer over said first and second portions of said first metal layer, wherein said second metal layer comprises gold;

after said forming said second metal layer, removing said photoresist layer;

after said removing said photoresist layer, removing said first metal layer not under said second metal layer such that said first metal layer remains under said second metal layer; and

after said removing said first metal layernot under said second metal layer, removing said sacrificial layer vertically under said remaining first metal layer and creating a void vertically under said remaining first metal layer.

2. The method of claim 1, wherein said forming said second metal layer comprises an electroplating process.

3. The method of claim 1, wherein said sacrificial layer comprises a polymer.

4. The method of claim 1, wherein said forming said sacrificial layer comprises a spin-coating process.

5. The method of claim 1 further comprising providing a transistor in or on said silicon substrate.

6. The method of claim 1, wherein said forming said first metal layer comprises a sputtering process.

7. The method of claim 1, wherein said forming said first metal layer comprises forming a gold layer comprising a first portion over said top surface of said sacrificial layer and at said sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer.

8. The method of claim 1, wherein said forming said first metal layer comprises forming a titanium-containing layer comprising a first portion over said top surface of said sacrificial layer and at said sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer.

9. A method for fabricating a circuit component, comprising:

providing a silicon substrate;

forming a sacrificial layer over said silicon substrate;

forming a first gold-containing layer comprising a first portion over a top surface of said sacrificial layer and at a sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer;

forming a photoresist layer on said first gold-containing layer, wherein an opening in said photoresist layer exposes said first and second portions of said first gold-containing layer;

after said forming said photoresist layer, electroplating a second gold-containing layer over said first and second portions of said first gold-containing layer;

after said electroplating said second gold-containing layer, removing said photoresist layer;

after said removing said photoresist layer, removing said first gold-containing layer not under said second gold-containing layer such that said first gold-containing layer remains under said second gold-containing layer; and

after said removing said first gold-containing layer not under said second gold-containing layer, removing said sacrificial layer vertically under said remaining first gold-containing layer and creating a void vertically under said remaining first gold-containing layer.

10. The method of claim 9, wherein said sacrificial layer comprises a polymer.

11. The method of claim 9, wherein said forming said sacrificial layer comprises a spin-coating process.

12. The method of claim 9 further comprising forming a titanium-containing layer comprising a first portion over said top surface of said sacrificial layer and at said sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer, followed by said forming said first gold-containing layer further on said titanium-containing layer.

27. The method of claim 9 further comprising providing a transistor in or on said silicon substrate.

13. A method for fabricating a circuit component, comprising:

providing a silicon substrate, a dielectric layer over said silicon substrate, a metal pad on said dielectric layer, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein an opening in said passivation layer is over a contact point of said metal pad, and said contact point is at a bottom of said opening;

forming a sacrificial layer having a portion directly on said passivation layer;

electroplating a metal layer comprising a first portion over a top surface of said sacrificial layer and at a sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer; and

after said electroplating said metal layer, removing said sacrificial layer vertically under said metal layer and creating a void vertically under said metal layer such that said metal layer is connected to said contact point through said opening.

14. The method of claim 13, wherein said sacrificial layer comprises a polymer.

15. The method of claim 13, wherein said forming said sacrificial layer comprises a spin-coating process.

16. The method of claim 13, wherein said electroplating said metal layer comprises electroplating a gold-containing layer comprising a first portion over said top surface of said sacrificial layer and at said sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer.

28. The method of claim 13, wherein said electroplating said metal layer comprises electroplating a copper-containing layer comprising a first portion over said top surface of said sacrificial layer and at said sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer.

29. The method of claim 13, wherein said electroplating said metal layer comprises electroplating a nickel-containing layer comprising a first portion over said top surface of said sacrificial layer and at said sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer.

17. A method for fabricating a circuit component, comprising:

providing a silicon substrate, multiple transistors in or on said silicon substrate, a dielectric layer over said silicon substrate, a metal pad on said dielectric layer, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein an opening in said passivation layer is over a contact point of said metal pad, and said contact point is at a bottom of said opening in said passivation layer;

forming a sacrificial layer having a portion directly on said passivation layer;

forming a first metal layer comprising a first portion over a top surface of said sacrificial layer and at a sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer;

forming a photoresist layer on said first metal layer, wherein an opening in said photoresist layer exposes said first and second portions of said first metal layer;

after said forming said photoresist layer, forming a second metal layer over said first and second portions of said first metal layer;

after said forming said second metal layer, removing said photoresist layer;

after said removing said photoresist layer, removing said first metal layer not under said second metal layer, wherein said first metal layer remains under said second metal layer; and

after said removing said first metal layer, not under said second metal layer, removing said sacrificial layer vertically under said remaining first metal layer and creating a void vertically under said remaining first metal layer.

18. The method of claim 17, wherein said forming said second metal layer comprises an electroplating process.

19. The method of claim 17, wherein said sacrificial layer comprises a polymer.

20. The method of claim 17, wherein said forming said sacrificial layer comprises a spin-coating process.

21. The method of claim 17, wherein said forming said second metal layer comprises forming a gold-containing layer over said first and second portions of said first metal layer.

22. The method of claim 17, wherein said forming said first metal layer comprises a sputtering process.

23. The method of claim 17, wherein said forming said first metal layer comprises forming a gold layer comprising a first portion over said top surface of said sacrificial layer and at said sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer.

24. The method of claim 17, wherein said forming said first metal layer comprises forming a titanium-containing layer comprising a first portion over said top surface of said sacrificial layer and at said sidewall of said sacrificial layer, and a second portion over said silicon substrate but not over said sacrificial layer.

25. The method of claim 17, wherein said forming said second metal layer comprises forming a copper-containing layer over said first and second portions of said first metal layer.

26. The method of claim 17, wherein said forming said second metal layer comprises forming a nickel-containing layer over said first and second portions of said first metal layer.

30. A method for fabricating a semiconductor chip, comprising:

providing a silicon substrate, multiple transistors in or on said silicon substrate, a dielectric layer over said silicon substrate, a metal pad on said dielectric layer, and a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein an opening in said passivation layer is over a contact point of said metal pad, and said contact point is at a bottom of said opening, wherein said passivation layer has a top surface with a first region, a second region and a third region between said first and second regions;

forming a polymer spacer on said third region but not over said first and second regions, wherein said polymer spacer has a first sidewall and a second sidewall opposite to said first sidewall;

forming a metal layer on said contact point, on said first and second regions, on said first and second sidewalls and on a top of said polymer spacer;

forming a gold-containing layer over said metal layer, over said contact point, over said first and second regions, at said first and second sidewalls and over said top of said polymer spacer; and

removing said metal layer not under said gold-containing layer such that said metal layer remains under said gold-containing layer and on said contact point, said first and second regions, said first and second sidewalls and said top of said polymer spacer, and said gold-containing layer is connected to said contact point through said opening, but does not connect said contact point to any other contact point at a bottom of another opening in said passivation layer.

32. The method of claim 30, wherein said forming said gold-containing layer comprises an electroless plating process.

33. The method of claim 30, wherein said forming said gold-containing layer comprises an electroplating process.

34. The method of claim 30, after said removing said metal layer not under said gold-containing layer, further comprising removing said polymer spacer vertically under said remaining metal layer and creating a void vertically under said remaining metal layer.

31. The method of caim 30, wherein said forming said metal layer comprises forming a titanium-containing layer on said contact point, on said first and second regions, on said first and second sidewalls and on said top of said polymer spacer.

35. A method for fabricating a semiconductor chip, comprising:

providing a silicon substrate, multiple transistors in or on said silicon substrate and a dielectric layer over said silicon substrate;

forming a sacrificial layer over said dielectric layer;

forming a first metal layer comprising a first portion over a top surface of said sacrificial layer and a second portion over said dielectric layer but not over said sacrificial layer;

forming a photoresist layer on said first metal layer, wherein an opening in said photoresist layer exposes said first and second portions of said first metal layer;

forming a second metal layer over said first and second portions of said first metal layer, wherein said second metal layer comprises gold;

after said forming said second metal layer, removing said photoresist layer;

after said removing said photoresist layer, removing said first metal layer not under said second metal layer such that said first metal layer remains under said second metal layer; and

after said removing said first metal layer not under said second metal layer, removing said sacrificial layer.

36. The method of claim 35, wherein said forming said second metal layer comprises an electroplating process.

37. The method of claim 35, wherein said forming said first metal layer comprises forming a titanium-containing layer and forming a gold layer on said titanium-containing layer.

38. The method of claim 35, wherein said sacrificial layer comprises a polymer.