Method for reducing silicide defects in integrated circuits

• US 7,960,283 B2
• Filed: 06/28/2010
• Issued: 06/14/2011
• Est. Priority Date: 05/21/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Ye, Jeff Jianhui, See, Alex K H, Liu, Huang, Koh, Hui Peng, Zhou, Mei Sheng, Cong, Hai, Lu, Wei, Hsia, Liang Choo
• Primary Examiner(s): Mandala; Victor
• Assistant Examiner(s): Moore; Whitney
• Application Number:
  US12/825,325
• Publication Number:
  US 20100267236A1
• Time in Patent Office: 351 Days
• Field of Search: 257382-384, 257/214, 257/754, 257/755, 257/757, 257/407, 257/412, 257/E29.139, 257/E29.161, 257/E21.199, 257/E21.158, 438/184, 438/231, 438/302, 438/303, 438/581, 438/586, 438/592, 438/595, 438/661, 438663-665, 438/655, 438/656, 438/659, 438/682
• US Class Current: 438/682
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

Claims

1. A method for forming a transistor in an integrated circuit (IC) comprising:

providing a substrate having a gate on the substrate, the gate having gate sidewalls, and diffusion regions in the substrate adjacent to the gate;

forming dielectric spacers on the gate sidewalls;

forming metal silicide contacts over the diffusion regions, wherein portions of the metal silicide contacts are covered by the spacers; and

pulling back the dielectric spacers to reduce stress on the metal silicide contacts.

2. The method of claim 1 wherein the dielectric spacers are pulled back such that outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts.

3. The method of claim 1 wherein pulling back the dielectric spacers comprises an anisotropic etch.

4. The method of claim 1 comprising:

cleaning the substrate surface after forming the dielectric spacers, wherein the cleaning forms undercut regions in a lower portion of the dielectric spacers such that edge portions of the metal silicide contacts in the undercut regions are covered by the spacers.

5. The method of claim 4 wherein pulling back the dielectric spacers is performed after formation of the metal silicide contacts to align outer walls of the dielectric spacers with edges of the metal silicide contacts.

6. The method of claim 4 wherein cleaning the substrate surface comprises wet cleaning using DHF in a dilute aqueous solution.

7. The method of claim 1 wherein forming the metal silicide contacts comprises performing first and second annealing processes.

8. The method of claim 7 wherein the first annealing process is conducted at a first temperature range and the second annealing process is conducted at a second temperature range that is higher than the first temperature range.

9. The method of claim 8 wherein pulling back the dielectric spacers is performed between the first and second annealing processes.

10. The method of claim 8 wherein pulling back the dielectric spacers is performed after the second annealing process.

11. The method of claim 1 wherein the metal silicide contacts comprise nickel or nickel alloy.

12. A method for reducing metal pipes comprising:

providing a feature on a substrate;

forming dielectric spacers on sidewalls of the feature;

forming metal silicide contacts on the substrate adjacent to the dielectric spacers, wherein portions of the metal silicide contacts are covered by the spacers; and

pulling back the dielectric spacers to reduce stress on the metal silicide contacts.

13. The method of claim 12 wherein the dielectric spacers are pulled back such that outer walls of the dielectric spacers are aligned with edges of the metal silicide contacts.

14. The method of claim 12 wherein pulling back the dielectric spacers comprises an anisotropic etch.

15. The method of claim 12 comprising:

cleaning the substrate surface after forming the dielectric spacers, wherein the cleaning forms undercut regions in a lower portion of the dielectric spacers such that edge portions of the metal silicide contacts in the undercut regions are covered by the spacers.

16. The method of claim 15 wherein pulling back the dielectric spacers is performed after formation of the metal silicide contacts to align outer walls of the dielectric spacers with edges of the metal silicide contacts.

17. The method of claim 15 wherein cleaning the substrate surface comprises wet cleaning using DHF in a dilute aqueous solution.

18. The method of claim 12 wherein forming the metal silicide contacts comprises performing first and second annealing processes.

19. The method of claim 18 wherein the first annealing process is conducted at a first temperature range and the second annealing process is conducted at a second temperature range that is higher than the first temperature range.

20. The method of claim 18 wherein pulling back the dielectric spacers is performed in between the first and second annealing processes.