Devices containing permanent charge

• US 7,960,783 B2
• Filed: 08/21/2009
• Issued: 06/14/2011
• Est. Priority Date: 08/25/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohammed N., Paul, Amit
• Primary Examiner(s): PRENTY, MARK V
• Application Number:
  US12/545,808
• Publication Number:
  US 20100084704A1
• Time in Patent Office: 662 Days
• Field of Search: 257/330, 257/341, 257/488, 257/490, 257/495, 257/E29.257
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2256 through the applied layer
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material.

Claims

1. A high-voltage solid-state device, comprising:

an array of active device portions, containing at least some trenches which have added permanent charge therein, and

are laterally surrounded, for the majority of their vertical extent, by semiconductor material which is doped with a first conductivity type; and

a termination structure which surrounds said array, and which includes a final dielectric trench containing permanent charge;

wherein said final dielectric trench is surrounded by said material of said first conductivity type, and wherein doping of said material tapers off laterally to a junction, and said material outside of said junction is predominantly of a second conductivity type.

2. The device of claim 1, wherein said permanent charge is provided by immobile cesium ions.

3. The device of claim 1, wherein said termination structure further comprises a field plate.

4. The device of claim 1, wherein said termination structure extends out toward the edge of the semiconductor material in which said device is built.

5. The device of claim 1, wherein said termination structure includes at least one diffused guard ring.

6. The device of claim 1, wherein said first conductivity type is p-type, and said termination structure includes at least one p-type ring diffusion.

7. The device of claim 1, wherein said junction is predominantly vertical.

8. The device of claim 1, wherein said first conductivity type is p-type.

9. The device of claim 1, wherein said trenches within said array include conductive gate electrodes.

10. The device of claim 1, wherein some of said trenches within said array include conductive gate electrodes, and others of said trenches within said array do not.

11. A high-voltage solid-state device, comprising:

an array of active device portions, containing at least some trenches which include gate electrodes, and

have added permanent charge therein, and

are laterally surrounded, for the majority of their vertical extent, by semiconductor material which is doped with a first conductivity type and is capacitively coupled, at least in part, to ones of said gate electrodes; and

a termination structure which surrounds said array, and which includes a final dielectric trench which contains permanent charge and which has approximately the same depth as said trenches in said array;

wherein said final dielectric trench is surrounded by said material of said first conductivity type, and wherein doping of said material tapers off laterally to a predominantly vertical junction, and said material outside of said junction is predominantly of a second conductivity type.

12. The device of claim 11, wherein said first conductivity type is p-type, and said termination structure includes at least one p-type ring diffusion.

13. The device of claim 11, wherein some of said trenches within said array include conductive gate electrodes, and others of said trenches within said array do not.

14. A high-voltage solid-state device, comprising:

an array of active device portions, containing

first trenches which have added permanent charge, and contain conductive gate electrodes, and are laterally surrounded, for at least some of their vertical extent, by semiconductor material which is doped with a first conductivity type; and

also

source diffusions of a second conductivity type, at least partly overlying said semiconductor material which laterally surrounds ones of said first trenches; and

second trenches which are different from said first trenches; and

a termination structure which laterally surrounds said array, and which includes a final dielectric trench which is also surrounded by said material of said first conductivity type, and wherein doping of said material tapers off laterally to a substantially vertical junction, and wherein said termination structure also contains peak-field-reducing structures outside said junction.

15. The device of claim 14, wherein said final trench is structurally similar to said first trenches, but not said second trenches.

16. The device of claim 14, wherein said final trench is structurally similar to said second trenches, but not to said first trenches.

17. The device of claim 14, wherein said termination structure includes at least one diffused guard ring.

18. The device of claim 14, wherein said first conductivity type is p-type, and said termination structure includes at least one p-type ring diffusion.

19. The device of claim 14, wherein said junction is vertical for the depth of said first trenches.