Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
First Claim
1. A semiconductor transistor, comprising:
- an insulating layer;
a fin, having opposing sidewalls and a top surface, the fin of a first material having a first silicon germanium content causing a first lattice spacing, above the insulating layer;
a layer of a second material covering the fin, the layer of the second material having a second silicon germanium content causing a second lattice spacing substantially larger than the first lattice spacing of the first material;
a dielectric layer, formed on the layer of the second material; and
a gate electrode with the dielectric layer between the gate electrode and the opposing sidewalls and the top surface of the fin.
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Abstract
A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
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Citations
10 Claims
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1. A semiconductor transistor, comprising:
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an insulating layer; a fin, having opposing sidewalls and a top surface, the fin of a first material having a first silicon germanium content causing a first lattice spacing, above the insulating layer; a layer of a second material covering the fin, the layer of the second material having a second silicon germanium content causing a second lattice spacing substantially larger than the first lattice spacing of the first material; a dielectric layer, formed on the layer of the second material; and a gate electrode with the dielectric layer between the gate electrode and the opposing sidewalls and the top surface of the fin. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor transistor structure, comprising:
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an insulating layer; a first fin on the insulating layer; a second fin on the insulating layer, wherein the first fin and the second fin are formed from a first material having a first lattice spacing; a second layer of a second material formed on a first fin, wherein the second layer of the second material has a second lattice spacing substantially larger than the first lattice spacing; and a third layer of a third material formed on a second fin, wherein the third material has a third lattice spacing substantially smaller than the first lattice spacing. - View Dependent Claims (8, 9, 10)
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Specification