Gate electrode stress control for finFET performance enhancement description

• US 7,960,801 B2
• Filed: 01/28/2010
• Issued: 06/14/2011
• Est. Priority Date: 11/03/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/695,660
• Publication Number:
  US 20100127327A1
• Time in Patent Office: 502 Days
• Field of Search: 257/64, 257/288, 257/347, 257/351, 257/401, 257/402, 257/412, 257/521, 257/527, 257/627, 257/628
• US Class Current: 257/401
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

Claims

1. An n-finFET semiconductor device comprising:

a substrate including at least one silicon semiconductor fin having a crystalline orientation of longitudinal (110), transverse (001) and vertical (1-10); and

a gate electrode with an intrinsic stress covering a channel region within the semiconductor fin, wherein the gate electrode induces at least one of a tensile vertical stress and a compressive transverse stress on the channel region to increase carrier mobility in the n-finFET semiconductor device.

2. The n-finFET semiconductor device of claim 1 wherein the substrate comprises a bulk semiconductor substrate.

3. The n-finFET semiconductor device of claim 1 wherein the substrate comprises a semiconductor-on-insulator semiconductor substrate.

4. The n-finFET semiconductor device of claim 1 wherein the intrinsic stress of the gate electrode ranges from 500 Mpa to 1500 MPa.

5. The n-finFET semiconductor device of claim 1 wherein the at least one silicon semiconductor fin has a vertical piezoresistance coefficient that is negative, and has a transverse piezoresistance coefficient that is positive.

6. The n-finFET semiconductor device of claim 5 wherein the vertical piezoresistance coefficient is −

17.6, and the transverse piezoresistance coefficient is 53.4.

11. The p-finFET semiconductor device of claim 1 wherein the at least one silicon semiconductor fin has a vertical piezoresistance coefficient that is negative, and has a transverse piezoresistance coefficient that is negative.

12. The p-finFET semiconductor device of claim 11 wherein the vertical piezoresistance coefficient is −

66.3, and the transverse piezoresistance coefficient is −

1.1.

7. A p-finFET semiconductor device comprising:

a substrate including at least one silicon semiconductor fin having a crystalline orientation of longitudinal (110), transverse (001) and vertical (1-10); and

a gate electrode with an intrinsic stress covering a channel region within the semiconductor fin, wherein the gate electrode induces a tensile vertical stress on the channel region to increase carrier mobility in the p-finFET semiconductor device.

8. The p-finFET semiconductor device of claim 7 wherein the substrate comprises a bulk semiconductor substrate.

9. The p-finFET semiconductor device of claim 7 wherein the substrate comprises a semiconductor-on-insulator semiconductor substrate.

10. The p-finFET semiconductor device of claim 7 wherein the intrinsic stress of the gate electrode ranges from 500 Mpa to 1500 MPa.