Methods and apparatus for multi-modal wafer testing

• US 7,960,986 B2
• Filed: 11/21/2008
• Issued: 06/14/2011
• Est. Priority Date: 06/06/2006
• Status: Active Grant

• Current Assignee: Shanghai Carson Semiconductor Company Limited
• Original Assignee: Advanced Inquiry Systems, Inc.
• Inventors: Johnson, Morgan T.
• Primary Examiner(s): Patel, Paresh
• Application Number:
  US12/275,226
• Publication Number:
  US 20090289645A1
• Time in Patent Office: 935 Days
• Field of Search: None
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

Access to integrated circuits of a wafer for concurrently performing two or more types of testing, is provided by bringing a wafer and an edge-extended wafer translator into an attached state. The edge-extended wafer translator having wafer-side contact terminals and inquiry-side contact terminals disposed thereon, a first set of wafer-side contact terminals being electrically coupled to a first set of inquiry-side contact terminals, and a second set of wafer-side contact terminals being electrically coupled to a second set of inquiry-side contact terminals. The edge-extended wafer translator having a central portion generally coextensive with the attached wafer, and an edge-extended portion extending beyond the boundary generally defined by the outer circumferential edge of the wafer. A first set of pads of at least one integrated circuit is electrically coupled to the first set of wafer-side contact terminals, and a second set of pads of the integrated circuit is electrically coupled to the second set of wafer-side contact terminals. The edge-extended wafer translator may be shaped such that its edge-extended portion is not coplanar with the central portion thereof.

Claims

1. An assembly for providing concurrent electrical access to one or more integrated circuits on a wafer, comprising:

an edge-extended wafer translator having a central portion, and an edge-extended portion vertically offset from the central portion;

a mounting fixture upon which the vertically offset edge-extended portion is disposed;

a first probe structure operable to contact a first plurality of inquiry-side contact terminals; and

a second probe structure operable to contact a second plurality of inquiry-side contact terminals;

wherein removably attaching the wafer to the central portion brings a first plurality of wafer-side contact terminals into electrical contact with a first set of pads on the wafer, and brings a second plurality of wafer-side contact terminals into electrical contact with a second set of pads on the wafer;

wherein the first plurality of wafer-side contact terminals are electrically connected to the first plurality of inquiry-side contact terminals disposed on the central portion of the edge-extended wafer translator, and the second plurality of wafer-side contacts are electrically connected to the second plurality of inquiry-side contact terminals disposed on the edge-extended portion of edge-extended wafer translator; and

wherein, during operation, the first probe structure is laterally movable relative to the mounting fixture and the second probe structure is fixed relative to the mounting fixture.

2. The assembly of claim 1, further comprising a wafer removably attached to the central portion of the edge-extended wafer translator.

3. The assembly of claim 2, further comprising a wafer chuck operable to position the wafer for removable attachment to the edge-extended wafer translator.

4. The assembly of claim 1, wherein the mounting fixture forms a portion of a wafer prober.

5. The assembly of claim 1, wherein the first probe structure comprises a probe card, and the second probe structure comprises DFT/BIST probe pins.

6. The assembly of claim 1, wherein the central portion of the edge-extended wafer translator is coextensive with the wafer.

7. The assembly of claim 1, further comprising at least one mechanism for substantially sealing the space between the wafer and a portion of the edge-extended wafer translator.

8. The assembly of claim 7, wherein the at least one mechanism comprises a gasket.

9. The assembly of claim 8, wherein the gasket comprises a pliable O-ring.

10. The assembly of claim 1, wherein the edge-extended wafer translator substantially matches the thermal expansion characteristics of the wafer.

11. An assembly for providing concurrent electrical access to one or more integrated circuits on a wafer, comprising:

an edge-extended wafer translator having a central portion, an edge-extended portion vertically offset from the central portion, and the edge-extended wafer translator further having a wafer-side and an inquiry-side;

a mounting fixture having an upper surface and a lower surface, the wafer-side of the vertically offset edge-extended portion of the edge-extended wafer translator disposed upon the upper surface of the mounting fixture;

a first probe structure operable to contact a first plurality of inquiry-side contact terminals; and

a second probe structure operable to contact a second plurality of inquiry-side contact terminals;

wherein removably attaching the wafer to the central portion brings a first plurality of wafer-side contact terminals into electrical contact with a first set of pads on the wafer, and brings a second plurality of wafer-side contact terminals into electrical contact with a second set of pads on the wafer;

wherein the first plurality of wafer-side contact terminals are electrically connected to the first plurality of inquiry-side contact terminals disposed on the central portion of the edge-extended wafer translator, and the second plurality of wafer-side contacts are electrically connected to the second plurality of inquiry-side contact terminals disposed on the edge-extended portion of edge-extended wafer translator; and

wherein, the first probe structure is laterally movable relative to the mounting fixture.

12. The assembly of claim 11, wherein the first probe structure is laterally movable relative to the mounting fixture during operation.

13. The assembly of claim 12, wherein, during operation, the second probe structure is fixed relative to the mounting fixture.

14. The assembly of claim 13, further comprising a wafer removably attached to the central portion of the edge-extended wafer translator.