Closed-grid bus architecture for wafer interconnect structure

• US 7,960,990 B2
• Filed: 04/20/2010
• Issued: 06/14/2011
• Est. Priority Date: 07/10/2000
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Long, John Matthew, Miller, Charles A.
• Primary Examiner(s): Nguyen; Vinh P
• Application Number:
  US12/763,907
• Publication Number:
  US 20100264947A1
• Time in Patent Office: 420 Days
• Field of Search: None
• US Class Current: 324/755.01
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/023 using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 1/0289 having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
• CPC Class Codes: H05K 2201/09254 Branched layout
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Claims

1. An interconnect structure for providing links between tester channels of a tester and integrated circuits for testing the integrated circuits, the interconnect structure comprising:

an electrical connection disposed on an upper surface and arranged to electrically connect to a tester channel when the interconnect structure is coupled to the tester;

a plurality of spring contacts disposed on a lower surface and arranged to electrically connect to pads of the integrated circuits when the interconnect structure and the integrated circuits are brought together;

a signal path electrically connecting the electrical connection to the plurality of spring contacts; and

a plurality of thin film resisters disposed within the signal path, wherein one of the thin film resistors is disposed between each one of the plurality of spring contacts and the electrical connection.

2. The interconnect structure of claim 1, further comprising:

a second electrical connection disposed on the upper surface and arranged to electrically connect to a second test channel;

a plurality of second spring contacts disposed on the lower surface and arranged to electrically connect to second pads of the integrated circuits;

a second signal path electrically connecting the second electrical connection to the second plurality of spring contacts; and

a second plurality of thin film resisters disposed within the second signal path, wherein one of the second thin film resistors is disposed between each one of the second plurality of spring contacts and the second electrical connection.

3. The interconnect structure of claim 1 further comprises a multilayer circuit board, wherein at least part of the signal path passes through the multilayer circuit board and the plurality of thin film resisters are disposed on an interior layer of the multilayer circuit board.

4. The interconnect structure of claim 1, wherein the signal path corresponds to a bus, and the plurality of spring contacts are arranged to contact corresponding pads of different integrated circuits disposed on a wafer.

5. The interconnect structure of claim 4, wherein the corresponding pads are any one of:

an address input/output and a data input/output.

6. An interconnect structure for providing links between tester channels of a tester and integrated circuits for testing the integrated circuits, the interconnect structure comprising:

a plurality of electrical connections disposed on an upper surface and arranged to electrically connect to corresponding ones of the tester channels when the interconnect structure is coupled to the tester;

a plurality of spring contacts disposed on a lower surface and arranged to electrically connect to pads of the integrated circuits when the interconnect structure and the integrated circuits are brought together;

a plurality of signal paths electrically connecting ones of the electrical connections to ones of the plurality of spring contacts, wherein ones of the signal paths are busses; and

a plurality of thin film resisters, wherein each one of the spring contacts that is electrically connected to a bus is isolated from the bus by one of the thin film resistors.

7. The interconnect structure of claim 6 further comprises a multilayer circuit board, wherein at least part of the signal paths pass through the multilayer circuit board and the plurality of thin film resisters are disposed on an interior layer of the multilayer circuit board.

8. The interconnect structure of claim 6, wherein each one of the spring contacts coupled to one of the busses corresponds to a pad of a different integrated circuit.

9. The interconnect structure of claim 8, wherein the pads are any one of:

an address input/output and a data input/output.