Closed-grid bus architecture for wafer interconnect structure
First Claim
1. An interconnect structure for providing links between tester channels of a tester and integrated circuits for testing the integrated circuits, the interconnect structure comprising:
- an electrical connection disposed on an upper surface and arranged to electrically connect to a tester channel when the interconnect structure is coupled to the tester;
a plurality of spring contacts disposed on a lower surface and arranged to electrically connect to pads of the integrated circuits when the interconnect structure and the integrated circuits are brought together;
a signal path electrically connecting the electrical connection to the plurality of spring contacts; and
a plurality of thin film resisters disposed within the signal path, wherein one of the thin film resistors is disposed between each one of the plurality of spring contacts and the electrical connection.
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Accused Products
Abstract
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.
68 Citations
9 Claims
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1. An interconnect structure for providing links between tester channels of a tester and integrated circuits for testing the integrated circuits, the interconnect structure comprising:
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an electrical connection disposed on an upper surface and arranged to electrically connect to a tester channel when the interconnect structure is coupled to the tester; a plurality of spring contacts disposed on a lower surface and arranged to electrically connect to pads of the integrated circuits when the interconnect structure and the integrated circuits are brought together; a signal path electrically connecting the electrical connection to the plurality of spring contacts; and a plurality of thin film resisters disposed within the signal path, wherein one of the thin film resistors is disposed between each one of the plurality of spring contacts and the electrical connection. - View Dependent Claims (2, 3, 4, 5)
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6. An interconnect structure for providing links between tester channels of a tester and integrated circuits for testing the integrated circuits, the interconnect structure comprising:
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a plurality of electrical connections disposed on an upper surface and arranged to electrically connect to corresponding ones of the tester channels when the interconnect structure is coupled to the tester; a plurality of spring contacts disposed on a lower surface and arranged to electrically connect to pads of the integrated circuits when the interconnect structure and the integrated circuits are brought together; a plurality of signal paths electrically connecting ones of the electrical connections to ones of the plurality of spring contacts, wherein ones of the signal paths are busses; and a plurality of thin film resisters, wherein each one of the spring contacts that is electrically connected to a bus is isolated from the bus by one of the thin film resistors. - View Dependent Claims (7, 8, 9)
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Specification