Semiconductor device and electronic apparatus having the same

• US 7,961,006 B2
• Filed: 01/25/2010
• Issued: 06/14/2011
• Est. Priority Date: 06/02/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi, Kimura, Hajime
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/692,893
• Publication Number:
  US 20100134708A1
• Time in Patent Office: 505 Days
• Field of Search: 326 82- 87, 324210-214
• US Class Current: 326/82
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

With an offset circuit including transistors of the same conductivity type, offset of an input signal is performed. Then, the input signal after the offset is supplied to a logic circuit including transistors of the same conductivity type as that of the offset circuit, thereby H and L levels of the input signal can be shifted at the same time. Further, since the offset circuit and the logic circuit are formed using the transistors of the same conductivity type, a display device can be manufactured at a low cost.

Claims

1. A display device comprising:

a first wiring configured to supply a first electric potential;

a second wiring configured to supply a second electric potential lower than the first electric potential;

a third wiring configured to supply a third electric potential higher than the second electric potential and lower than first electric potential;

a fourth wiring configured to supply a fourth electric potential higher than the second electric potential and lower than the third electric potential;

an offset circuit comprising;

a first capacitor electrically connected to the third wiring;

a second capacitor electrically connected to the fourth wiring, wherein capacitance of the second capacitor is smaller than that of the first capacitor;

a first transistor including a gate electrode, a first electrode and a second electrode, wherein the gate electrode is electrically connected to the first capacitor, the first electrode of the first transistor is electrically connected to the second wiring, and the second electrode of the first transistor is electrically connected to the second capacitor;

a second transistor including a gate electrode, a first electrode and a second electrode, wherein the gate electrode of the second transistor is electrically connected to the second capacitor and the second electrode of the first transistor, a first electrode of the second transistor is electrically connected to the second wiring, and the second electrode of the second transistor is electrically connected to the first capacitor and the gate electrode of the first transistor;

an output terminal electrically connected to the second capacitor, the second electrode of the first transistor and the second electrode of the second transistor, wherein the output terminal is configured to output an offset signal by shifting levels of the third wiring and the fourth wiring; and

a logic circuit electrically connected to the output terminal, wherein the logic circuit is configured to be driven by the offset signal and outputs a signal.

2. The display device according to claim 1, wherein conductivity type of the first transistor and the second transistor are the same.

3. The display device according to claim 1, wherein the first transistor and the second transistor are P-channel transistors.

4. A display device comprising:

a first wiring configured to supply a first electric potential;

a second wiring configured to supply a second electric potential lower than the first electric potential;

a third wiring configured to supply a third electric potential higher than the second electric potential and lower than first electric potential;

a fourth wiring configured to supply a fourth electric potential higher than the second electric potential and lower than the third electric potential;

an offset circuit comprising;

a first capacitor electrically connected to the third wiring;

a second capacitor electrically connected to the fourth wiring, wherein capacitance of the second capacitor is smaller than that of the first capacitor;

a first transistor including a gate electrode, a first electrode and a second electrode, wherein the gate electrode is electrically connected to the first capacitor, the first electrode of the first transistor is electrically connected to the second wiring, and the second electrode of the first transistor is electrically connected to the second capacitor;

a second transistor including a gate electrode, a first electrode and a second electrode, wherein the gate electrode of the second transistor is electrically connected to the second capacitor and the second electrode of the first transistor, a first electrode of the second transistor is electrically connected to the second wiring, and the second electrode of the second transistor is electrically connected to the first capacitor and the gate electrode of the first transistor;

an output terminal electrically connected to the second capacitor, the second electrode of the first transistor and the second electrode of the second transistor, wherein the output terminal is configured to output an offset signal by shifting levels of the third wiring and the fourth wiring; and

a logic circuit electrically connected to the output terminal, wherein the logic circuit is configured to be driven by the offset signal and outputs a signal,

wherein the first transistor and the second transistor include In, Ga, Zn and O.

5. The display device according to claim 4, wherein conductivity type of the first transistor and the second transistor are the same.

6. The display device according to claim 4, wherein the first transistor and the second transistor are P-channel transistors.

7. A display device comprising:

a first wiring configured to supply a first electric potential;

a second wiring configured to supply a second electric potential higher than the first electric potential;

a third wiring configured to supply a third electric potential lower than the second electric potential and higher than first electric potential;

a fourth wiring configured to supply a fourth electric potential lower than the second electric potential and higher than the third electric potential;

an offset circuit comprising;

a first capacitor electrically connected to the third wiring;

a second capacitor electrically connected to the fourth wiring, wherein capacitance of the second capacitor is smaller than that of the first capacitor;

a first transistor including a gate electrode, a first electrode and a second electrode, wherein the gate electrode is electrically connected to the first capacitor, the first electrode of the first transistor is electrically connected to the second wiring, and the second electrode of the first transistor is electrically connected to the second capacitor;

a second transistor including a gate electrode, a first electrode and a second electrode, wherein the gate electrode of the second transistor is electrically connected to the second capacitor and the second electrode of the first transistor, a first electrode of the second transistor is electrically connected to the second wiring, and the second electrode of the second transistor is electrically connected to the first capacitor and the gate electrode of the first transistor;

an output terminal electrically connected to the second capacitor, the second electrode of the first transistor and the second electrode of the second transistor, wherein the output terminal is configured to output an offset signal by shifting levels of the third wiring and the fourth wiring; and

a logic circuit electrically connected to the output terminal, wherein the logic circuit is configured to be driven by the offset signal and outputs a signal.

8. The display device according to claim 7, wherein conductivity type of the first transistor and the second transistor are the same.

9. The display device according to claim 7, wherein the first transistor and the second transistor are N-channel transistors.

10. A display device comprising:

a first wiring configured to supply a first electric potential;

a second wiring configured to supply a second electric potential higher than the first electric potential;

a third wiring configured to supply a third electric potential lower than the second electric potential and higher than first electric potential;

a fourth wiring configured to supply a fourth electric potential lower than the second electric potential and higher than the third electric potential;

an offset circuit comprising;

a first capacitor electrically connected to the third wiring;

a second capacitor electrically connected to the fourth wiring, wherein capacitance of the second capacitor is smaller than that of the first capacitor;

a first transistor including a gate electrode, a first electrode and a second electrode, wherein the gate electrode is electrically connected to the first capacitor, the first electrode of the first transistor is electrically connected to the second wiring, and the second electrode of the first transistor is electrically connected to the second capacitor;

a second transistor including a gate electrode, a first electrode and a second electrode, wherein the gate electrode of the second transistor is electrically connected to the second capacitor and the second electrode of the first transistor, a first electrode of the second transistor is electrically connected to the second wiring, and the second electrode of the second transistor is electrically connected to the first capacitor and the gate electrode of the first transistor;

an output terminal electrically connected to the second capacitor, the second electrode of the first transistor and the second electrode of the second transistor, wherein the output terminal is configured to output an offset signal by shifting levels of the third wiring and the fourth wiring; and

a logic circuit electrically connected to the output terminal, wherein the logic circuit is configured to be driven by the offset signal and outputs a signal,

wherein the first transistor and the second transistor include In, Ga, Zn and O.

11. The display device according to claim 10, wherein conductivity type of the first transistor and the second transistor are the same.

12. The display device according to claim 10, wherein the first transistor and the second transistor are N-channel transistors.