RF power amplifier integrated circuit and unit cell

• US 7,961,052 B2
• Filed: 10/28/2009
• Issued: 06/14/2011
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Li, Yang, Bacon, Peter, Broughton, Robert, Calanca, Neil, Bonkowski, James
• Primary Examiner(s): CHOE, HENRY
• Application Number:
  US12/589,800
• Publication Number:
  US 20110095824A1
• Time in Patent Office: 594 Days
• Field of Search: 330/307, 330/311
• US Class Current: 330/307
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H03F 3/195 in integrated circuits

Abstract

A novel RF power amplifier integrated circuit (PA IC), unit cell, and method for amplifying RF signals are disclosed. One embodiment of a PA IC includes at least two linear arrays comprising transistor device units, and at least one linear array comprising capacitors. The transistor device units include source nodes that are jointly coupled to a source bus, and selected gate nodes that are jointly coupled to a gate bus. First electrodes of the capacitors are also jointly coupled to the source bus, and second electrodes of the capacitors are jointly coupled to the gate bus. Each linear array comprising capacitors is disposed between at least two linear arrays comprising transistor device units. In one embodiment, the PA IC includes unit cells. In some embodiments, each unit cell comprises two transistor device units and one or more capacitors. The capacitors are disposed between the transistor device units. The unit cells are disposed in linear arrays so that the transistor device units are disposed in linear arrays and the capacitors are disposed in linear arrays.

Claims

1. An RF power amplifier integrated circuit, comprising:

a) a plurality of linear arrays of transistor device units, wherein each transistor device unit comprises at least one source node and at least one first gate node;

b) at least one source bus, wherein the at least one source bus is operably coupled to the at least one source node of each transistor device unit;

c) at least one first gate bus, wherein the at least one first gate bus is operably coupled to the at least one first gate node of each transistor device unit; and

,

d) a least one linear array of capacitors, wherein a first electrode of each of the capacitors is operably coupled to the at least one source bus, and wherein a second electrode of each of the capacitors is operably coupled to the at least one first gate bus, and wherein the at least one linear array of capacitors is disposed between two of the linear arrays of transistor device units.

2. The RF power amplifier integrated circuit of claim 1, further comprising unit cells, wherein each of the unit cells comprises a plurality of the transistor device units and at least one of the capacitors, and wherein the at least one of the capacitors is disposed between and operably coupled to at least two of the transistor device units.

3. The RF power amplifier integrated circuit of claim 1, wherein the transistor device units comprise a plurality of transistor sub-units operably coupled together, and wherein each sub-unit comprises a plurality of transistors operably coupled together.

4. The RF power amplifier integrated circuit of claim 1, wherein the transistor device units comprise at least one interdigitated transistor.

5. The RF power amplifier integrated circuit of claim 4, wherein the at least one interdigitated transistor comprises:

a) a source contact;

b) a drain contact; and

,

c) two interdigitated gate contacts disposed between the source contact and the drain contact.

6. The RF power amplifier integrated circuit of claim 1, wherein the at least one source bus is disposed on top of the at least one linear array of capacitors.

7. The RF power amplifier integrated circuit of claim 6, wherein the at least one source bus comprises a metal layer.

8. The RF power amplifier integrated circuit of claim 1, wherein the at least one first gate bus is disposed on the bottom of the at the least one linear array of capacitors.

9. The RF power amplifier integrated circuit of claim 1, further comprising at least one drain bus, and wherein the transistor device units comprise at least one drain node, and wherein the least one drain bus is operably coupled to the at least one drain node and is disposed on top of at least one of the linear arrays of transistor device units.

10. The RF power amplifier integrated circuit of claim 2, further comprising at least one second gate bus, and wherein the unit cells comprise at least one second gate node operably coupled to the at least one second gate bus, and wherein the at least one second gate bus is not electrically coupled to the capacitors, and wherein the at least one second gate bus is disposed between two linear arrays of the unit cells.

11. The RF power amplifier integrated circuit of claim 1, further comprising at least one contact pad, wherein the at least one contact pad is coupled to the RF power amplifier integrated circuit to convey heat generated by the transistor device units, and wherein the at least one contact pad is disposed between two linear arrays of the transistor device units.

12. The RF power amplifier integrated circuit of claim 11, wherein a method for contacting the at least one contact pad is selected from the following methods:

a wire bonding method and a flip-chip mounting method.

13. The RF power amplifier integrated circuit of claim 12, wherein the flip-chip mounting method comprises at least one the following:

solder bumps, gold balls, and Cu pillars.

14. The RF power amplifier integrated circuit of claim 1, wherein the capacitors comprise at least one of the following capacitor types:

metal-insulator-metal capacitors, metal-oxide-semiconductor capacitors, and vertical native capacitors.

15. The RF power amplifier integrated circuit of claim 1, wherein the integrated circuit is fabricated on a substrate having a resistivity greater than 10 ohm-cm.

16. The RF power amplifier integrated circuit of claim 1, wherein the integrated circuit is fabricated on a substrate selected from the following substrates:

silicon-on-sapphire, SIMOX, and silicon-on-glass.

17. A method for amplifying RF signals, comprising the steps of:

a) providing an input RF signal to an input bus operably coupled to input nodes of a plurality of linear arrays of transistor device units, wherein two linear arrays of the transistor device units are operably coupled to at least one linear array of the capacitors, and wherein the at least one linear array of capacitors is disposed between two of the linear arrays of transistor device units; and

,

b) providing an output RF signal via an output bus operably coupled to output nodes of the two linear arrays of transistor device units.

18. The method of claim 17, further comprising the step of removing heat from the vicinity of the transistor device units via at least one contact pad, wherein the at least one contact pad is disposed in a region between the two linear arrays of transistor device units, and is operably coupled to the region between the two linear arrays of transistor device units in order to convey heat generated by the transistor device units.

19. The method of claim 18, wherein a method for contacting the at least one contact pad is selected from the following methods:

a wire bonding method and a flip-chip mounting method.

20. The method of claim 19, wherein the flip-chip mounting method comprises at least one the following:

solder bumps, gold balls, and Cu pillars.

21. A unit cell for use in implementing an RF power amplifier integrated circuit, comprising:

at least two transistor device units (TDUs), wherein the TDUs comprise a plurality of transistor sub-units, and wherein the transistor sub-units include at least two transistors coupled together in a series configuration, and wherein the at least two TDUs comprise source nodes (SN) and gate nodes (GN) coupled to the sources and drains of the at least two transistors; and

a coupling capacitor disposed between the at least two TDUs, wherein the coupling capacitor has a first electrode and a second electrode disposed on opposite sides of the coupling capacitor, and wherein the first electrode is coupled to the source nodes (SN) and wherein the second electrode is coupled to the gate nodes (GN).

22. The unit cell of claim 21, wherein the unit cell comprises three or more TDUs coupled together in series, and wherein the TDUs are coupled to a selected number of coupling capacitors, wherein the coupling capacitors are coupled in a parallel configuration, and wherein first electrodes of the coupling capacitors are coupled to the source nodes (SN) and wherein second electrodes of the coupling capacitors are coupled to the gate nodes (GN).

23. The unit cell of claim 21, wherein the sub-units are coupled together in one of the following possible electrical configurations:

a parallel configuration;

a serial configuration;

or as a combination of both parallel and serial configurations.

24. The unit cell of claim 21, wherein the TDUs comprise interdigitated transistor devices.

25. The unit cell of claim 21, wherein the sub-units comprise interdigitated transistor devices.