Variable resistive memory punchthrough access method

• US 7,961,497 B2
• Filed: 10/14/2010
• Issued: 06/14/2011
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Liu, Hongyue, Lee, Brian, Carter, Andrew John Gjevre, Khoury, Maroun Georges
• Primary Examiner(s): Lam; David
• Application Number:
  US12/904,288
• Publication Number:
  US 20110026307A1
• Time in Patent Office: 243 Days
• Field of Search: 365/148, 365/158, 365/163, 365/203, 365/189.09
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

Claims

1. A method comprising:

precharging a plurality of bit lines and a plurality of source lines to a precharge voltage being less than a punchthrough voltage of a transistor, the plurality of source lines intersecting with the plurality of bit lines and forming a cross-point array, and a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising a variable resistive data cell and the transistor, the transistor is electrically connected between the variable resistive data cell and one of the plurality of source lines; and

writing a first data state to one or more variable resistive data cells along a selected bit line by applying the punchthrough voltage across the selected bit line and one or more selected source lines to pass a first data state write current through the transistor by merging a source depletion region and a drain depletion region in the transistor substrate in punchthrough mode.

2. A method according to claim 1, further comprising writing a second data state to one or more variable resistive data cells along a selected bit line by applying the punchthrough voltage across the selected bit line and one or more selected source lines to pass a second data state write current through the transistor in punchthrough mode, the second data state write current opposing the first data state write current.

3. A method according to claim 2, wherein the first data state write current has about the same magnitude as the second data state write current.

4. A method according to claim 1, wherein the transistor is a NMOS transistor or a PMOS transistor.

5. A method according to claim 1, wherein the variable resistive data cell is a magnetic tunnel junction data cell.

6. A method according to claim 5, wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.

7. A method according to claim 1, further comprising passing a read current through the variable resistive data cell by activating a gate of the transistor.

8. A method according to claim 1, further comprising passing a read current through the variable resistive data cell, the read current passing through the transistor in punchthrough mode.

9. A method according to claim 1, wherein the first data state write current and the second data state write current is formed by a voltage difference across the source depletion region and the drain depletion region and having a magnitude equal to or greater than the punchthrough voltage for the transistor.

10. A method according to claim 1, wherein the precharge voltage is in a range from 40 to 60% of the punchthrough voltage.

11. A method according to claim 1, wherein the precharge voltage is about 50% of the punchthrough voltage.

12. A method comprising:

precharging a plurality of bit lines and a plurality of source lines to a precharge voltage being less than a punchthrough voltage of a transistor, the plurality of source lines intersecting with the plurality of bit lines and forming a cross-point array, and a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising a variable resistive data cell and the transistor, the transistor is electrically connected between the variable resistive data cell and one of the plurality of source lines; and

writing a first data state to one or more variable resistive data cells along a selected bit line by applying the punchthrough voltage across the selected bit line and one or more selected source lines.

13. A method according to claim 12, wherein the precharge voltage is in a range from 40 to 60% of the punchthrough voltage.

14. A method according to claim 12, wherein the transistor is a NMOS transistor or a PMOS transistor.

15. A method according to claim 12, wherein the variable resistive data cell is a magnetic tunnel junction data cell.

16. A method according to claim 15, wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.

17. A method according to claim 12, further comprising passing a read current through the variable resistive data cell, the read current passing through the transistor in punchthrough mode.