Integrated circuits to control access to multiple layers of memory in a solid state drive

• US 7,961,510 B2
• Filed: 12/02/2008
• Issued: 06/14/2011
• Est. Priority Date: 02/06/2008
• Status: Expired due to Fees

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Primary Examiner(s): Luu; Pho M
• Assistant Examiner(s): BUI, THA-O H
• Application Number:
  US12/315,361
• Publication Number:
  US 20090198485A1
• Time in Patent Office: 924 Days
• Field of Search: 365/185.01, 365/51, 365/63, 365/230.01, 365/230.03, 703/24, 711/163, 711/156, 711/152, 711/145
• US Class Current: 365/185.01
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

Claims

1. A solid state drive that emulates a hard disk drive, comprising:

a substrate including circuitry fabricated in a logic layer of the substrate;

a memory in contact with and fabricated directly above the substrate, the memory including a plurality of vertically stacked memory layers that are in contact with one another, each memory layer is positioned in a memory plane that is distinct from memory planes of other memory layers, and each memory layer including at least one non-volatile two-terminal cross-point memory array that is electrically coupled with the circuitry, at least a portion of the circuitry is configured to perform data operations on the at least one non-volatile two-terminal cross-point memory array, each non-volatile two-terminal cross-point memory array including a plurality of two-terminal memory cells; and

a memory access circuit included in the circuitry and configured to enable or disable data operations access to a first subset of the plurality of the two-terminal memory cells in response to a plurality of signals electrically coupled with the memory access circuit, the plurality of signals including access control data and a controllable access address, the access control data is stored in an access control memory included in a second subset of the plurality of the two-terminal memory cells, the memory access circuit including an emulation interface configured to emulate a hard disk drive.

2. The solid state drive of claim 1, wherein at least one two-terminal memory cell in the first subset of the plurality of two-terminal memory cells resides in a different memory plane in the memory than at least one two-terminal memory cell in the access control memory.

3. The solid state drive of claim 1, wherein the plurality of two-terminal memory cells comprise non-volatile two-terminal third dimension memory cells.

4. The solid state drive of claim 1, wherein the memory access circuit is further configured to communicate with any of the plurality of vertically stacked memory layers of the memory to determine the access control data for the first subset of the plurality of two-terminal memory cells.

5. The solid state drive of claim 1, wherein the memory access circuit comprises a circuit portion and a memory portion, the circuit portion is positioned in the logic layer and the memory portion is positioned in one or more of the plurality of vertically stacked memory layers.

6. The solid state drive of claim 1, wherein the plurality of vertically stacked memory layers are configurable to include an amount of the second subset of the plurality of two-terminal memory cells, the amount being distributed in a vertical arrangement.

7. The solid state drive of claim 6, wherein the vertical arrangement comprises a variable amount of the second subset of the plurality of two-terminal memory cells without substantially increasing a size of the substrate.

8. The solid state drive of claim 1, wherein the memory access circuit is further configured to detect the data operations access to the first subset of the plurality of two-terminal memory cells and to restrict the data operations access to the first subset of the plurality of two-terminal memory cells substantially in parallel with the data operations access.

9. The solid state drive of claim 1, wherein the data operations access includes either a write operation or read operation, or both, in association with the first subset of the plurality of two-terminal memory cells.

10. The circuit of claim 1, wherein the plurality of vertically stacked memory layers are formed directly on top of the logic layer using a fabrication process that was used to form the circuitry in logic layer.

11. The solid state drive of claim 1 and further comprising:

an access interrupter included in the circuitry and configured to interrupt application of an access voltage to the first subset of the plurality of two-terminal memory cells, wherein interrupting the application of the access voltage is operative to disable the data operations access.

12. The solid state drive of claim 11, wherein the access interrupter is further configured to interrupt application of a write access voltage to the first subset of the plurality of two-terminal memory cells, if the data operations access is a write operation, and to interrupt application of a read access voltage to the first subset of the plurality of two-terminal memory cells, if the data operations access is a read operation.

13. The solid state drive of claim 1 and further comprising:

an override access controller included in the circuitry and configured to neutralize the access control data.

14. The solid state drive of claim 1, wherein the first subset of the plurality of two-terminal memory cells constitute a row.

15. The solid state drive of claim 14, wherein the row comprises a sector.

16. The solid state drive of claim 1, wherein the first subset of the plurality of two-terminal memory cells constitute a portion of a row.

17. The solid state drive of claim 16, wherein the portion comprises a byte.

18. The solid state drive of claim 1, wherein the first subset of the plurality of two-terminal memory cells constitute a block of memory.

19. The solid state drive of claim 1, wherein the second subset of the plurality of two-terminal memory cells comprises a write protect bit configurable to permit or prohibit write data access to the first subset of the plurality of two-terminal memory cells.

20. The solid state drive of claim 1, wherein the second subset of the plurality of two-terminal memory cells comprises a read protect bit configurable to permit or prohibit read data access from the first subset of the plurality of two-terminal memory cells.

21. The solid state drive of claim 1, wherein the plurality of vertically stacked memory layers further comprise a vertically-stacked arrangement of non-volatile two-terminal third dimension memory cells.

22. The solid state drive of claim 1, wherein each two-terminal memory cell includes a two-terminal memory element including mobile ions and operative to change a conductivity profile in response to a write voltage applied across a first terminal and a second terminal of the two-terminal memory element,

application of the write voltage operative to transport the mobile ions and cause the change in the conductivity profile, and the change in the conductivity profile is indicative of stored data written to the two-terminal memory element by the application of the write voltage.

23. The solid state drive of claim 1, wherein the plurality of vertically stacked memory layers include a plurality of two-terminal memory elements, each two-terminal memory element including an electrolytic tunnel barrier in contact with and electrically in series with a mixed valence conductive oxide, each two-terminal memory element including a first terminal and a second terminal,

a programming voltage applied across the first and second terminals operative to transport mobile ions from the mixed valence conductive oxide to the electrolytic tunnel barrier to store data as a programmed state, and

an erase voltage applied across the first and second terminals operative to transport the mobile ions from the electrolytic tunnel barrier to the mixed valence conductive oxide to store data as an erased state.

24. The solid state drive of claim 1, wherein the memory comprises a third dimension memory array including a two-terminal stacked cross-point array.

25. The solid state drive of claim 24, where the two-terminal stacked cross-point array includes a plurality of two-terminal memory elements, each two-terminal memory element including an electrolytic tunnel barrier in contact with and electrically in series with a mixed valence conductive oxide, each two-terminal memory element including a first terminal and a second terminal,

a programming voltage applied across the first and second terminals operative to transport mobile ions from the mixed valence conductive oxide to the electrolytic tunnel barrier to store data as a programmed state, and

an erase voltage applied across the first and second terminals operative to transport the mobile ions from the electrolytic tunnel barrier to the mixed valence conductive oxide to store data as an erased state.

26. The solid state drive of claim 1, where the emulation interface comprises a NOR-type interface.

27. The solid state drive of claim 1, where the emulation interface comprises a NAND-type interface.