Methods, circuits, and systems to select memory regions

• US 7,961,542 B2
• Filed: 10/19/2009
• Issued: 06/14/2011
• Est. Priority Date: 05/21/2007
• Status: Active Grant

• Current Assignee: Scott Smith
• Original Assignee: Scott Smith
• Inventors: Smith, Scott
• Primary Examiner(s): Hoang; Huan
• Assistant Examiner(s): RADKE, JAY W
• Application Number:
  US12/581,747
• Publication Number:
  US 20100034034A1
• Time in Patent Office: 603 Days
• Field of Search: 365/200, 365/201, 365/230.03, 365/222, 365226-229
• US Class Current: 365/222
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.

Claims

1. A memory module comprising:

a plurality of memory devices; and

a memory hub configured to receive memory requests corresponding to a first region of one or more of the plurality of memory devices, the memory hub operable to communicate the memory requests to the one or more of the plurality of memory devices and transmit memory data from the one or more of the plurality of memory devices in response to at least one of the memory requests; and

a selection block configured to receive the memory requests corresponding to the first region of one or more of the plurality of memory devices and to receive an input signal indicating a number of defective cells that are replaced by redundant cells in at least one region of one or more of the plurality of memory devices selectable by the selection block relative to that of at least another region of the one or more of the plurality of memory devices selectable by the selection block, the selection block operable to map the memory requests to a second region of the one or more of the plurality of memory devices based on the input signal.

2. A processor-based system comprising:

a processing apparatus operable to process data and to provide memory commands and addresses;

a system controller in communication with the processing apparatus, the system controller operable to receive and transmit memory commands, addresses and data;

a plurality of memory devices in communication with the system controller, each of the plurality of memory devices operable to receive memory commands, addresses, and write data for storage in at least one of the memory devices, and to transmit read data from the memory devices to the system controller; and

a selection block configured to receive an address signal indicative of a region of memory devices, the selection block being operable to generate a selection signal to map the address signal indicative of the region of memory devices to a physical location of the plurality of memory devices, the selection block further being operable to generate the selection signal on the basis of the number of defective cells that are replaced by redundant cells in the physical location of the plurality of memory devices relative to that of at least one other region selectable by the selection block.

3. A memory device comprising:

a plurality of memory cells organized logically in a plurality of rows and partitioned into a plurality of individually selectable regions, each region comprising at least a portion of said plurality of rows; and

a row selection block in communication with the plurality of rows and configured to receive an address signal indicative of a first region of the plurality of regions, individually selectable by the row selection block;

wherein the row selection block is operable to generate a selection signal based at least in part on an identification of a number of defective cells that are replaced by redundant cells in the first region relative to a number of defective cells of a second region of the plurality of regions selectable by the row selection block.

4. The memory device of claim 3, wherein the selection signal is configured to reduce a delay in accessing memory location selected by the address signal.

5. The memory device of claim 3, wherein the row selection block is further configured to generate the selection signal based at least in part on a signal indicating a match between at least a portion of the address signal and a predetermined address location, the predetermined address location related to a defective memory cell.

6. The memory device of claim 5, wherein the row selection block further comprises an activation module operable to generate a control signal to select a memory location within the second region of the plurality of regions responsive to the signal indicating a match.

7. The memory device of claim 3 further comprising a refresh control block in communication with the array selection block, the refresh control block operable to assign a region of the memory cells to be refreshed in response to the selection of a partial array self-refresh mode.

8. The memory device of claim 7, wherein:

the refresh control block further comprises activate command logic; and

the row selection block further comprises an activation module in communication with the activate command logic, the activation module operable to enable a selection of the selected memory cells responsive to receiving a control signal from the activate command logic.

9. A memory device having a plurality of memory cells logically partitioned into a plurality of individually selectable regions, the memory device comprising:

an address register block configured to receive external address signals and operable to generate internal address signals corresponding to the external address signals; and

a selection block in communication with the address register block and configured to effect selection of the plurality of individually selectable regions;

wherein;

the selection block is configured to receive the internal address signals and an input signal indicating a plurality of defective cells that are replaced by redundant cells in at least a first region of the plurality of regions selectable by the selection block relative to that of at least a second region of the plurality of regions selectable by the selection block; and

the selection block is operable to map the internal address signals to a physical location within the plurality of memory cells based at least in part on the input signal.

10. The memory device of claim 9, wherein the selection block is further configured to generate a selection signal based at least in part on a signal indicating a match between at least a portion of the address signal and a predetermined address location, the predetermined address location related to a defective memory cell.

11. The memory device of claim 10, wherein the selection block farther comprises an activation module operable to generate a control signal to select an memory location within the second region of the plurality of regions responsive to the match signal.

12. The memory device of claim 9, wherein the selection block is operable to map the internal address signals to a physical location within the plurality of memory cells based on a refresh characteristic.

13. The memory device of claim 9, further comprising a refresh control block in communication with the address register block and configured to receive the internal address signals, the refresh control block operable to generate a control signal to select memory cells at the physical location to be refreshed in a partial array self-refresh mode.

14. The memory device of claim 13, wherein the selection block further comprises an activation module, the activation module being operable to enable a selection of the selected memory cells responsive to receiving the control signal from the refresh control block.

15. The memory device of claim 14, wherein the refresh characteristic comprise a time between refresh that is double the standard time between refresh.