System and method for adjusting multiple control loops using common criteria

• US 7,961,823 B2
• Filed: 06/29/2004
• Issued: 06/14/2011
• Est. Priority Date: 06/02/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Currivan, Bruce, Kolze, Thomas, Momtaz, Afshin
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US10/879,673
• Publication Number:
  US 20050271137A1
• Time in Patent Office: 2,541 Days
• Field of Search: 375/232, 375/233, 375/326, 375/327, 375/340, 375/346, 375/348, 375/371, 375/373, 375/376
• US Class Current: 375/346
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Data error such as mean square error may be reduced in a system such as a communication receiver using a dithering algorithm that adjusts one or more parameters in the system. The dithering algorithm may be applied to more than one parameter in a nested manner. The dithering algorithm may be modified to immediately check the MSE after a parameter has been adjusted.

Claims

1. A method of processing a signal comprising:

receiving the signal;

processing, using a plurality of control loops, the received signal in accordance with a plurality of respective control signals;

acquiring a plurality of error signals from the processed signal; and

adjusting the respective control signals for the plurality of control loops in accordance with the plurality of error signals and a common error measurement criteria applied to each of the plurality of error signals.

2. The method of claim 1 wherein the error measurement criteria comprises a square error.

3. The method of claim 1 wherein the error measurement criteria comprises a mean square error.

4. The method of claim 1 wherein processing comprises clock recovery and at least one of the control signals provides a phase adjust for the clock recovery.

5. The method of claim 4 wherein processing further comprises decision feedback equalization and at least one of the control signals provides an equalization coefficient for the decision feedback equalization.

6. The method of claim 4 wherein processing further comprises continuous time filtering and at least one of the control signals provides a bandwidth adjust for the continuous time filtering.

7. The method of claim 4 wherein processing further comprises generating a sampling clock signal for an analog to digital converter and at least one of the control signals provides a phase adjust for generating the sampling clock signal.

8. The method of claim 1 wherein adjusting the respective control signals comprises performing dithering on the respective control signals.

9. The method of claim 1 wherein adjusting the respective control signals comprises performing nested dithering on the respective control signals.

10. The method of claim 1 wherein acquiring the plurality of error signals comprises sampling the processed signal.

11. The method of claim 1 wherein acquiring the plurality of error signals comprises sampling a soft decision signal associated with the received signal.

12. A system for processing a received signal comprising:

at least one processing component configured to process the received signal, using a plurality of control loops, in accordance with a plurality of respective control signals;

a plurality of error acquisition components configured to acquire a plurality of error signals from the processed signal;

at least one error calculation component configured to calculate at least one measure of error in accordance with the plurality of error signals and a common error measurement criteria applied to each of the plurality of error signals; and

at least one control signal generator configured to adjust the respective control signals in accordance with the at least one measure of error and the common error measurement criteria.

13. The system of claim 12 wherein the error measurement criteria comprises a square error.

14. The system of claim 12 wherein the error measurement criteria comprises a mean square error.

15. The system of claim 12 wherein the at least one processing component comprises a clock recovery circuit and at least one of the control signals provides a phase adjust for the clock recovery circuit.

16. The system of claim 15 wherein the at least one processing component further comprises a decision feedback equalizer and at least one of the control signals provides an equalization coefficient for the decision feedback equalizer.

17. The system of claim 15 wherein the at least one processing component further comprises a continuous time filter and at least one of the control signals provides a bandwidth adjust for the continuous time filter.

18. The system of claim 15 wherein the at least one processing component further comprises an analog to digital converter for sampling the processed signal and a lock loop circuit configured to generate a sampling clock signal for the analog to digital converter, wherein at least one of the control signals provides a phase adjust for the lock loop circuit.

19. The system of claim 18 wherein the processed signal comprises a soft decision signal.

20. The system of claim 12 wherein the at least one control signal generator is configured to adjust at least one of the control signals in accordance with a dithering algorithm.

21. The system of claim 12 wherein the at least one control signal generator is configured to adjust two or more of the plurality of control signals in accordance with a nested dithering algorithm.

22. A method of processing a signal comprising:

receiving the signal;

processing the received signal, using a plurality of control loops, in accordance with a plurality of respective control signals, the processing comprising;

recovering at least one clock signal in accordance with at least a first one of the control signals; and

applying adaptive equalization in accordance with at least a second one of the control signals;

acquiring a plurality of error signals from the processed signal; and

respectively adjusting, based on the plurality of error signals, a common error measurement criteria applied to each of the plurality of error signals, the at least first one of the control signals and the at least second one of the control signals to minimize a square error.

23. The method of claim 22 wherein the at least first one of the control signals is adjusted in accordance with dithering.

24. The method of claim 23 wherein the adaptive equalization comprises feed forward equalization or decision feedback equalization.

25. The method of claim 24 wherein the square error comprises a mean square error.

26. The method of claim 24 wherein the at least second one of the control signals is adjusted in accordance with a least mean square algorithm or dithering.

27. The method of claim 23 wherein the at least second one of the control signals is adjusted in accordance with a least mean square algorithm or dithering.

28. The method of claim 22 wherein the at least second one of the control signals is adjusted in accordance with a least mean square algorithm or dithering.