Clock and data recovery circuit having wide phase margin
First Claim
1. A clock and data recovery (CDR) circuit comprising:
- a sampler configured to sample serial data in response to a recovery clock signal to generate a serial sampling pulse;
a CDR loop configured to transform the serial sampling pulse into parallel data, to generate k phase signals simultaneously with a first speed based on the parallel data, and to generate a phase control signal with a second speed k times higher than the first speed based on the k phase signals, k being an integer greater than 1; and
a phase interpolator configured to generate the recovery clock signal fed to the sampler by controlling a phase of a reference clock signal in response to the phase control signal from the CDR loop,wherein the CDR loop is configured to transform the serial sampling pulse into the parallel data of n bits, to generate the k phase signals with the first speed based on a plurality of data groups in response to a clock signal having a 1/n frequency relative to the recovery clock signal, and to generate the phase control signal with the second speed based on the k phase signals, the parallel data of n bits being divided into the plurality of data groups.
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Abstract
A clock and data recovery (CDR) circuit includes a sampler, a CDR loop and a phase interpolator. The sampler samples serial data in response to a recovery clock signal to generate a serial sampling pulse. The CDR loop transforms the serial sampling pulse into parallel data, generates a plurality of phase signals with a first speed based on the parallel data, and generates a phase control signal with a second speed higher than the first speed based on the plurality of phase signals. The phase interpolator generates the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal. Therefore, the CDR circuit may recover data and a clock with a relatively high speed.
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Citations
30 Claims
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1. A clock and data recovery (CDR) circuit comprising:
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a sampler configured to sample serial data in response to a recovery clock signal to generate a serial sampling pulse; a CDR loop configured to transform the serial sampling pulse into parallel data, to generate k phase signals simultaneously with a first speed based on the parallel data, and to generate a phase control signal with a second speed k times higher than the first speed based on the k phase signals, k being an integer greater than 1; and a phase interpolator configured to generate the recovery clock signal fed to the sampler by controlling a phase of a reference clock signal in response to the phase control signal from the CDR loop, wherein the CDR loop is configured to transform the serial sampling pulse into the parallel data of n bits, to generate the k phase signals with the first speed based on a plurality of data groups in response to a clock signal having a 1/n frequency relative to the recovery clock signal, and to generate the phase control signal with the second speed based on the k phase signals, the parallel data of n bits being divided into the plurality of data groups. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of recovering a clock and data, the method comprising:
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sampling serial data in response to a recovery clock signal to generate a serial sampling pulse; transforming the serial sampling pulse into parallel data; generating k phase signals simultaneously with a first speed based on the parallel data, k being an integer greater than 1; generating a phase control signal with a second speed k times higher than the first speed based on the k phase signals; and generating the recovery clock signal by controlling a phase of a reference clock signal in response to the phase control signal, the reference signal being externally provide, wherein the parallel data is n-bit parallel data, and generating the k phase signals with the first speed comprises generating the k phase signals with the first speed based on a plurality of data groups in response to a clock signal having a 1/n frequency relative to the recovery clock signal, the n-bit parallel data being divided into the data groups. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification