×

Clock and data recovery circuit having wide phase margin

  • US 7,961,830 B2
  • Filed: 08/23/2006
  • Issued: 06/14/2011
  • Est. Priority Date: 08/24/2005
  • Status: Expired due to Fees
First Claim
Patent Images

1. A clock and data recovery (CDR) circuit comprising:

  • a sampler configured to sample serial data in response to a recovery clock signal to generate a serial sampling pulse;

    a CDR loop configured to transform the serial sampling pulse into parallel data, to generate k phase signals simultaneously with a first speed based on the parallel data, and to generate a phase control signal with a second speed k times higher than the first speed based on the k phase signals, k being an integer greater than 1; and

    a phase interpolator configured to generate the recovery clock signal fed to the sampler by controlling a phase of a reference clock signal in response to the phase control signal from the CDR loop,wherein the CDR loop is configured to transform the serial sampling pulse into the parallel data of n bits, to generate the k phase signals with the first speed based on a plurality of data groups in response to a clock signal having a 1/n frequency relative to the recovery clock signal, and to generate the phase control signal with the second speed based on the k phase signals, the parallel data of n bits being divided into the plurality of data groups.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×