Design structure for compensating for variances of a buried resistor in an integrated circuit

• US 7,962,322 B2
• Filed: 06/09/2008
• Issued: 06/14/2011
• Est. Priority Date: 05/19/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Awad, Mariette, Feng, Kai Di, Awad, Elie
• Primary Examiner(s): Rodriguez; Paul L
• Assistant Examiner(s): Kim; Eunhee
• Application Number:
  US12/135,232
• Publication Number:
  US 20080234997A1
• Time in Patent Office: 1,100 Days
• Field of Search: 703/14, 716/2, 327/513
• US Class Current: 703/14
• CPC Class Codes: G05F 1/561 Voltage to current converters amplifiers H03F
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.

Claims

1. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium;

the design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit for compensating for a variance in the resistance of a buried resistor, and wherein said design structure further comprises;

a waveform that is representative of the thermal characteristics of a first and second buried resistor; and

functions to compensate for the variance in resistance according to the waveform the compensation circuit (500) further comprises a first and second thermal compensation unit (502, 504), a first and second inverter (INVA, INVB), and a differential driver (510);

the differential driver (510) further comprising at least a first and second pFET (PA, PB), and a first and second nFET (NA, NB), the first and second pFET (PA, PB) are coupled in series with a voltage supply (VDD) and the first and second buried resistor (506, 508) and the first and second nFET (NA, NB) respectively;

the first thermal compensation unit (502) comprises a fast response circuit (512), a slow response circuit (514), and an amplifying circuit (516);

the slow response circuit (514) comprises a third pFET (Pl) coupled in series with a third resistor (Rl1) coupled in series with a first capacitor (Cl), a fifth resistor (Rl2) coupled in series to a third nFET (Nl), the fifth resistor (Rl2) and the third nFET (Nl) are coupled in parallel to the first capacitor (Cl) and further coupled to ground;

the third pFET (Pl) further coupled to the output of the first inverter (INVA), receives a first inverter signal at its gate;

an eighth resistor (R2) is further coupled to the outputs of the third resistor (Rl1) and the first capacitor (Cl) and feeds a first operational amplifier (516A), which in turn couples to the gate of the first pFET (PA) of the differential driver (510);

the fast response circuit (512) comprising a fourth pFET (Pf) whose gate is coupled to the output of the first inverter (INVA) and the drain is coupled to a fourth resistor (Rf1), which is further coupled to a second capacitor (Cr) and ground;

a sixth resistor (Rf2) is coupled in series to a fourth nFET (Nf) and are subsequently coupled in parallel with the second capacitor (Cr);

a ninth resistor (R3) is coupled to the fourth resistor (Rf1) and the second capacitor (Cr), the ninth resistor (R3) is further coupled in series to a seventh resistor (R1), which is further coupled to the gate of the first pFET (PA), thereby altering the resistance of the first pFET (PA) to compensate for variance in resistance of first resistor (506).

2. The design structure of claim 1, wherein the machine-executable representation of a circuit comprises:

waveform is coupled to the input of the first inverter (INVA).

3. The design structure of claim 1, wherein the thermal characteristics is the thermal time constant of the buried resistor.

4. The design structure of claim 3 wherein the thermal time constant is the thermal behavior of the first or second resistor over a specific period of time.

5. The design structure of claim 4 wherein the specific period of time represents at least two phases of the thermal response where the temperature of the first or second resistor increases significantly when compared to a second periods of time.

6. The design structure of claim 1, wherein the design structure comprises a netlist.

7. The design structure of claim 1, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

8. The design structure of claim 1, wherein the design structure resides in a programmable gate array.