Division with rectangular multiplier supporting multiple precisions and operand types

0Associated
Cases 
0Associated
Defendants 
0Accused
Products 
4Forward
Citations 
0
Petitions 
1
Assignment
First Claim
1. A method implemented by a floating point unit of a processor, comprising:
 determining a first precision indicator;
estimating a reciprocal [X_{0}] of a divisor to determine a reciprocal estimate;
determining a first product [D_{0}] based on a rectangular multiplication of the divisor and the reciprocal estimate;
determining a first complement value [R_{0}] based on a complement of the first product;
determining a second product [N_{0}] based on a rectangular multiplication of the reciprocal estimate and a dividend; and
determining a quotient of the divisor and the dividend at a rectangular multiplier based on the second product, the precision indicator, and a portion of the first complement value.
1 Assignment
0 Petitions
Accused Products
Abstract
A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floatingpoint number. The division is performed at a rectangular multiplier using the Goldschmidt or NewtonRaphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.
12 Citations
View as Search Results
Microarchitecture for floating point fused multiplyadd with exponent scaling  
Patent #
US 9,110,713 B2
Filed 08/30/2012

Current Assignee
Qualcomm Inc.

Sponsoring Entity
Qualcomm Inc.

Microarchitecture for floating point fused multiplyadd with exponent scaling  
Patent #
US 9,841,948 B2
Filed 08/12/2015

Current Assignee
Qualcomm Inc.

Sponsoring Entity
Qualcomm Inc.

Processor for realizing at least two categories of functions  
Patent #
US 10,372,359 B2
Filed 05/10/2017

Current Assignee
ChengDu HaiCun IP Technology LLC

Sponsoring Entity
ChengDu HaiCun IP Technology LLC

Configurable processor with inpackage lookup table  
Patent #
US 10,445,067 B2
Filed 11/28/2018

Current Assignee
Guobiao Zhang, Hangzhou Haicun Information Technology Co. Ltd.

Sponsoring Entity
Hangzhou Haicun Information Technology Co. Ltd.

System and method for multiprecision division  
Patent #
US 7,738,657 B2
Filed 08/31/2006

Current Assignee
Intel Corporation

Sponsoring Entity
Intel Corporation

Efficient hardware divide operation  
Patent #
US 7,599,982 B1
Filed 09/08/2005

Current Assignee
Oracle America Inc.

Sponsoring Entity
Oracle America Inc.

Processing unit having decimal floatingpoint divider using NewtonRaphson iteration  
Patent #
US 20060064454A1
Filed 11/05/2004

Current Assignee
Wisconsin Alumni Research Foundation

Sponsoring Entity
Wisconsin Alumni Research Foundation

Pipelined multiplicative division with IEEE rounding  
Patent #
US 20040128338A1
Filed 10/29/2003

Current Assignee
Guy Even, PeterMichael Seidel

Sponsoring Entity
Guy Even, PeterMichael Seidel

Bipartite lookup table with output values having minimized absolute error  
Patent #
US 6,223,192 B1
Filed 06/16/1998

Current Assignee
GlobalFoundries Inc.

Sponsoring Entity
Advanced Micro Devices Inc.

Method and apparatus for performining floating point division  
Patent #
US 5,249,149 A
Filed 09/03/1991

Current Assignee
International Business Machines Corporation

Sponsoring Entity
International Business Machines Corporation

Bile acid derivatives, process for their preparation and use of these compounds as pharmaceuticals  
Patent #
US 5,250,524 A
Filed 12/04/1991

Current Assignee
Hoechst Aktiengesellschaft

Sponsoring Entity
Hoechst Aktiengesellschaft

Floating point/integer processor with divide and square root functions  
Patent #
US 4,878,190 A
Filed 01/29/1988

Current Assignee
Texas Instruments Inc.

Sponsoring Entity
Texas Instruments Inc.

20 Claims
 1. A method implemented by a floating point unit of a processor, comprising:
determining a first precision indicator; estimating a reciprocal [X_{0}] of a divisor to determine a reciprocal estimate; determining a first product [D_{0}] based on a rectangular multiplication of the divisor and the reciprocal estimate; determining a first complement value [R_{0}] based on a complement of the first product; determining a second product [N_{0}] based on a rectangular multiplication of the reciprocal estimate and a dividend; and determining a quotient of the divisor and the dividend at a rectangular multiplier based on the second product, the precision indicator, and a portion of the first complement value.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
 13. A method implemented by a floating point unit of a processor, comprising:
determining a first precision indicator; estimating a reciprocal of a divisor to determine a reciprocal estimate; determining a first product based on a multiplication of the reciprocal estimate and the divisor; determining a first complement value based on a complement of the first product; determining a second product based on a rectangular multiplication of the first complement value and the reciprocal estimate; determining a quotient of the divisor and the dividend at a rectangular multiplier based on a portion of the second product, the precision indicator, and the dividend.  View Dependent Claims (14, 15, 16, 17, 18)
 19. A floating point unit, comprising:
an input configured to receive a first precision indicator, a divisor, and a dividend; a lookup table configured to provide a reciprocal estimate based on a reciprocal of a divisor; a multiplier coupled to the lookup table and to the input, the multiplier configured to; determine a first product based on a multiplication of the divisor and the reciprocal estimate; determine a first complement value based on a complement of the first product; determine a second product based on a multiplication of the reciprocal estimate and a dividend; and determine a quotient of the divisor and the dividend based on the second product, the precision indicator, and a portion of the first complement value; and an output configured to provide the quotient.  View Dependent Claims (20)
1 Specification
The present disclosure relates to data processors and more particularly to floating point division operations on a data processor.
Data processors typically employ a floatingpoint unit (FPU) to perform floating point arithmetic. An FPU performs arithmetic operations such as addition, subtraction, multiplication, and division. Typically, a division operation requires the FPU to execute several operations, such as several multiplication and addition operations. The faster the FPU can execute a division operation, the faster and more efficiently the data processor can execute instructions. Accordingly, there is a need for an improved method of performing a division operation on an FPU.
The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
A method for performing division using a rectangular multiplier of a floatingpoint unit is disclosed. The method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floatingpoint number. The division is performed at a rectangular multiplier using the Goldschmidt or NewtonRaphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.
Referring to
The fetch stages 121 are illustrated as having a bidirectional connection to the cache 110 in that the fetch stages 121 are able to provide an address to the cache 110 and receive data based on the address. The fetch stages 121 also include an output. The dispatch stage 123 includes an input connected to the output of the fetch stages 121 and three outputs. The execution unit 124 includes an input connected to a first output of the dispatch stage 123 and an output. The execution unit 125 includes an input connected to a second output of the dispatch stage 123 and an output. The floatingpoint unit 126 includes an input connected to a third output of the dispatch stage 123 and an output. The post execution stages 128 include an input connected to the output of the execution unit 124, an input connected to the output of the execution unit 125, and an input connected to the output of the floatingpoint unit 126.
The cache 110 stores data for the instruction pipeline 105, including instruction data and operand data. It will be appreciated that although the cache 110 is illustrated as a single cache, it can represent multiple caches, such as separate caches for instruction data and operand data. In addition, the cache 110 may be accessible to other stages of the instruction pipeline 105, even though specific connections to the stages are not illustrated. For example, the execution units, such as the execution units 124 and 125, may be able to access the cache 110 to retrieve and store data.
During operation, the instruction pipeline 105 executes instructions at the data processor 100. To execute an instruction, the fetch stages 121 fetch instruction data from the cache 110. The fetch stages 121 decode the instruction data to obtain instruction information and, based on the instruction information, retrieve operand data from the cache 110. For example, in the case of a division instruction, the fetch stages 121 can retrieve the divisor and dividend from the cache 110.
The fetch stages 121 provides the instruction information and the operand data to the execution unit 124, the execution unit 125, or the floatingpoint unit 126 for execution. For example, if the instruction information indicates that the instruction requires a floating point operation, the instruction information and the operand data is provided to the floatingpoint unit 126.
The execution units 124 and 125, as well as the floatingpoint unit 126, provide the instruction information to the postexecution stages 128, which provides postexecution processing of the information. For example, the postexecution stages 128 can retire instructions, detect exceptions resulting from execution of the instructions, and the like.
The floatingpoint unit 126 executes instructions that require floating point operations, including addition, subtraction, multiplication, and division. The floatingpoint unit 126 includes a multiplier 130 to execute multiplication and division operations. In a particular embodiment, the multiplier 130 is a rectangular multiplier. A rectangular multiplier is characterized by having input operands of different sizes. For example, a 27×76 rectangular multiplier uses one operand of 27 bits and another of 76 bits. To execute a division operation, the floatingpoint unit 126 receives operand information from the dispatch stage 123, including a divisor and dividend. The dispatch stage 123 also provides instruction information, including a precision indicator to indicate whether the quotient should be a single precision value, a double precision value, or an extended precision value according to a specific standard, such as the IEEE754 Standard for Binary Floating Point Arithmetic. The precision indicator can include precision control information that indicates the desired level of precision of the quotient, as well as operand type information that indicates the precision level of the division operands.
In one embodiment, the floatingpoint unit 126 uses a Goldschmidt algorithm to perform division. The Goldschmidt algorithm computes the quotient Q=A/B by determining an estimate of the divisor'"'"'s reciprocal:
The following values are then determined:
N_{0}=X_{0}×A
D_{0}=X_{0}×B
R_{0}=2−D_{0 }
Subsequently, m−1 iterations are performed to calculate the following values:
N_{i+1}=R_{i}×N_{i }
D_{i+1}=R_{i}×D_{i }
R_{i+1}==2−D_{i−1 }
Once the m−1 iterations have been performed, the quotient Q is obtained as follows:
Q=N_{m+1}×R_{m+1 }
The number of iterations depends on the desired level of precision of the quotient Q as well as the accuracy of the estimate X_{0}. Accordingly, the less accurate the estimate X_{0 }and the higher the desired level of precision for the quotient Q, the greater the number of iterations performed before the quotient is determined.
In a particular embodiment, reduced values for R_{i}, including R_{0}, are used to calculate the N_{i }and D_{i }values and the quotient Q. As used herein, the term reduced means that one or more of the most significant bits, one or more of the least significant bits, or both are removed from a binary value. For example, the value R_{0 }may be a 76 bit value, and can be reduced by removing its least significant bits so that the reduced value is a 30 bit value. In addition, the R_{i }values may be reduced by different amounts for different iterations. For example, the value R_{0 }may be reduced to a 30 bit value while the value R_{1 }is reduced to a 60 bit value. By reducing the values for R_{i}, the division operations can be executed more efficiently at the multiplier 130 than with a multiplier that uses operands of equal sizes, while still achieving the desired level of precision for the quotient Q.
In another embodiment, the floatingpoint unit 126 uses a NewtonRaphson algorithm to determine the quotient Q=A/B. The floatingpoint unit determines the estimate of the divisor'"'"'s reciprocal:
and performs m iterations of the following equations:
R_{i}=2−X_{i}×B
X_{i+1}=X_{i}×R_{i }
After m iterations of these equations, X_{m }is multiplied by A to obtain the quotient Q. The number of iterations depends on the desired level of precision of the quotient Q as well as the accuracy of the estimate X_{0}.
In a particular embodiment, reduced values for R_{i}, and X_{i }are used to calculate the R_{i }and X_{i+1 }values and the quotient Q. In addition, the values may be reduced by different amounts for different iterations. By reducing the values for R_{i }and X_{i}, the division operations can be executed more efficiently at the multiplier 130 while still achieving the desired level of precision for the quotient Q.
Referring to
At block 202 input values are received, including a dividend A, a divisor B, a precision control indicator PC, an operand type indicator OT, and a rounding control indicator RC. The operand type indicator OT indicates whether the operands, including dividend A and the divisor B are single precision operands, double precision operands, or extended precision operands. The precision control information PC indicates the desired precision of the quotient when the operand type indicator OT indicates the operands are extended precision values. The rounding control indicator RC indicates whether the quotient Q_{f }should be rounded to the nearesteven, rounded toward zero, rounded toward minus infinity, or rounded toward plus infinity.
At block 204, the reciprocal estimate (X_{0}) of the divisor B is determined. The reciprocal estimate can be determined using a lookup table or other method. In a particular embodiment, the reciprocal estimate is determined using 2^{10 }by 16 and 2^{10 }by 7 bipartite tables to provide a reciprocal estimate accurate to at least 14.94 bits.
At block 206, values D_{0}, R_{0}, and N_{0 }are calculated. The value D_{0 }is calculated by performing a rectangular multiplication of the value X_{0 }and the divisor B. As used herein, the term “rectangular multiplication” refers to a multiplication using operands of different sizes. For example, a 27×76 rectangular multiplier performs a multiplication of a first operand with a size of 27 bits and a second operand with a size of 76 bits. In a preferred embodiment, the size of the first operand can be increased by iteratively performing multiplication operations at the rectangular multiplier. For example, the 27×76 rectangular multiplier can perform a 54×76 rectangular multiply be executing two iterative multiplications and one addition at the multiplier.
At block 206, the value R_{0 }is determined by calculating the 1'"'"'s compliment of D_{0}. The value N_{0 }is determined by performing a rectangular multiplication of the dividend A and the value X_{0}. In an exemplary embodiment where the reciprocal estimate X_{0 }is accurate to at least 14.94 bits, the values D_{0 }and N_{0 }are accurate to at least 27 bits.
At block 208, it is determined whether the operand type indicator indicates that the received operands are single precision values. If so, the method flow proceeds to block 210 and a value Q_{i }is determined based on the value N_{0 }and a value based on a portion of the value R_{0}. In a particular embodiment, the value R_{0 }is reduced by removing one or more of its least significant bits to form a reduced complement value. The value Q_{i }is determined by performing a rectangular multiplication of the value N_{0 }with the reduced complement value R_{0}. By using a reduced complement value, the multiplication can be performed with fewer iterations at the rectangular multiplier, thereby improving the efficiency of the division operation while still obtaining a desired level of precision of the quotient.
In another embodiment, the value R_{0 }is reduced by removing one or more most significant bits and one or more least significant bits from the value to form a reduced R_{0 }value. The value Q_{i }is determined by performing a fused rectangular multiplication and add operation, where a rectangular multiplication is performed using the truncated R_{0 }value and the value N_{0 }and the result is added to the value N_{0}. In a particular embodiment, the value R_{0 }is a 76 bit value and the truncated R_{0 }value is formed by bits 1339 of the value R_{0}.
At block 212 the value Q_{i }is rounded, based on the rounding control RC, to 24 bits of precision to obtain the single precision floatingpoint quotient Q_{f}. To determine how the quotient will be rounded, a remainder REM is determined by performing a rectangular multiplication of the divisor B by the value Q_{i}, and subtracting the result from the dividend A. The remainder REM indicates if the value Q_{i }is greater than, less than, or equal to the true quotient Q. In an exemplary embodiment, in response to the rounding control indicator RC indicating the result Q_{f }should not be less than the quotient Q, the rounding ensures that the single precision result Q_{f }is greater than or equal to the quotient Q. In an alternative embodiment, in response to the rounding control indicator RC indicating the result Q_{f }should not be more than the quotient Q, the rounding can ensure that the single precision result Q_{f }is less than or equal to the quotient Q. At block 226, the rounded single precision quotient value Q_{f }is provided.
Returning to block 208, if it is determined that the operand type indicator OT indicates that the operands are not single precision values, the method flow moves to block 216. At block 216, it is determined whether the operand type indicator OT indicates that the operands are extended precision values and whether the precision control indicates that the quotient result should be a single precision value. If so, the method flow moves to block 228, described below. If not, the method flow moves to block 218, and a value D_{1}, a value R_{1}, and a value N_{1 }are determined. In one embodiment, the value D_{1 }is calculated by removing one or more of the least significant bits from the value R_{0 }to form a reduced complement value and performing a rectangular multiplication of the values D_{0 }and the reduced complement value based on the value R_{0}. In a particular embodiment, the value R_{0 }is a 76 bit value and the reduced complement value is formed by the 54 most significant bits of R_{0}. In addition, the value N_{1 }is calculated by performing a rectangular multiplication of the values N_{0 }and the reduced complement value R_{0}. The value R_{1 }is determined by computing the complement of the value D_{1}.
In an alternative embodiment, the reduced complement value is formed by removing one or more of the least significant bits and one or more of the most significant bits of the value R_{0}. In a particular embodiment, R_{0 }is a 76 bit value and the reduced complement value is formed by bits 1339 of the value R_{0}. The value D_{1 }is calculated by performing a multiplyadd operation at a rectangular multiplier with the reduced complement value and the value D_{0}. The value N_{1 }is calculated by performing a multiplyadd operation at a rectangular multiplier with the reduced complement value and the value D_{0}. The value R_{1 }is determined by determining the complement of the value D_{1}.
At block 220, it is determined whether the operand type indicator OT indicates that the operand types are double precision values. If so, the method flow moves to block 222. At block 222, a quotient value Q_{i }is calculated. In one embodiment, the quotient value Q_{i }is calculated by performing a rectangular multiplication of the values R_{1 }and N_{1}.
In another embodiment, a reduced complement value is formed by removing one or more least significant bits from the value R_{1}. In a particular embodiment, R_{0 }is a 76 bit value and the reduced complement value is formed by bits 2675 of the value R_{0}. The quotient value Q_{i }is calculated by performing a multiplyadd operation at a rectangular multiplier using the reduced complement value and the value N_{1}.
At block 224, a remainder REM is determined by performing a rectangular multiplication of the quotient value Q_{i }and the divisor B and subtracting the result from the dividend A. The remainder REM indicates if the value Q_{i }is greater than, less than, or equal to the quotient Q. Based on this information, and the rounding control indicator RC, the quotient value Q_{i }is rounded to obtain the quotient Q_{f}. For example, in response to the rounding control indicator RC indicating the result Q_{f }should not be less than the quotient Q, the rounding ensures that the single precision result Q_{f }is greater than or equal to the quotient Q. In an alternative embodiment, in response to the rounding control indicator RC indicating the quotient value Q_{f }should not be more than the quotient Q, the rounding can ensure that the single precision quotient value Q_{f }is less than or equal to the quotient Q. At block 226, the quotient value result Q_{f }is provided.
Returning to block 220, if the operand type indicator OT does not indicate that the operands are double precision operands, the method flow moves to block 228. At block 228, it is determined whether the precision control indicator PC indicates that the quotient value should be a single precision value. If not, the method flow moves to block 230.
At block 230, it is determined whether the precision control indicator PC indicates that the quotient value should be a double precision value. If not, the method flow moves to block 232. At block 232, values N_{2}, R_{2 }and D_{2 }are calculated. In a particular embodiment, the value N_{2 }is calculated by performing a rectangular multiplication of the values R_{1 }and N_{1}, the value D_{2 }is calculated by performing a rectangular multiplication of the values R_{1 }and D_{1}, and the value R_{2 }is calculated by determining a complement value of the value D_{2}.
In another embodiment, a reduced R_{1 }value is formed by removing one or more of the least significant bits and one or more most significant bits of the value R_{1}. In a particular embodiment, the reduced R_{1 }value is the value of bits 2675 of the value R_{1}. The value N_{2 }is calculated by performing a multiplyadd operation using the reduced R_{1 }value and the value N_{1}. The value D_{2 }is calculated by performing a multiplyadd operation using the reduced R_{1 }value and the value D_{1}. The value R_{2 }is calculated by determining a complement value of the value D_{2}.
The method flow moves to block 234, and a quotient value Q_{i }is determined by performing a rectangular multiplication operation on the value R_{2 }and the value N_{2}. The method flow moves to block 240, and a remainder REM is calculated by performing a rectangular multiplication of the divisor B and the value Q_{i }and subtracting the result from the dividend A. The remainder REM indicates if the value Q_{i }is greater than, less than, or equal to the quotient Q. Based on the remainder REM and the rounding control indicator RC, the quotient Q_{f }is determined. In an exemplary embodiment, in response to the rounding control indicator RC indicating the result Q_{f }should not be less than the quotient Q, the rounding ensures that the single precision result Q_{f }is greater than or equal to the quotient Q. In an alternative embodiment, in response to the rounding control indicator RC indicating the result Q_{f }should not be more than the quotient Q, the rounding can ensure that the single precision result Q_{f }is less than or equal to the quotient Q. The method flow proceeds to block 226 and the quotient Q_{f }is provided.
At block 230, in response to the operand type indicator OT indicating the operands are double precision operands, the method flow moves to block 238. At block 238, the quotient value Q_{i }is calculated. In a particular embodiment, the quotient Q_{i }is calculated by performing a rectangular multiplication on the values N_{1 }and R_{1}.
In another embodiment, a reduced complement value is formed by removing one or more most significant bits from the value R and the quotient value Q_{i }is calculated by performing a multiplyadd operation at a rectangular multiplier using the reduced complement value and the value N_{1}. In a particular embodiment, R_{0 }is a 76 bit value and the reduced complement value is formed by bits 2675 of the value R_{0}.
At block 228, in response to the operand type indicator OT indicating the operands are single precision operands, the method flow moves to block 236. At block 236, the quotient value Q_{i }is calculated. In a particular embodiment, the quotient value Q_{i }is determined based on the value N_{0 }and a value based on a portion of the value R_{0}. In a particular embodiment, the value R_{0 }is reduced by removing one or more of its least significant bits to form a reduced complement value. The value Q_{i }is determined by performing a rectangular multiplication of the value N_{0 }with the reduced complement value.
In another embodiment, the value R_{0 }is reduced by removing one or more most significant bits and one or more least significant bits from the value to form a reduced R_{0 }value. The value Q_{i }is determined by performing a rectangular multiplication and add operation, where a rectangular multiplication is performed using the reduced R_{0 }value and the value N_{0 }and the result is shifted and added to the value N_{0}. In a particular embodiment, the value R_{0 }is a 76 bit value and the reduced R_{0 }value is formed by bits 1339 of the value R_{0}.
Referring to
At block 304, the reciprocal estimate (X_{0}) of the divisor B is determined. The reciprocal estimate can be determined using a look up table or other method. In a particular embodiment, the reciprocal estimate is determined using 2^{10 }by 16 and 2^{10 }by 7 bipartite tables to provide a reciprocal estimate accurate to at least 14.94 bits.
At block 306, the value R_{0 }is determined by performing a rectangular multiplication of the divisor B and the reciprocal estimate X_{0 }and calculating the 1'"'"'s compliment of the result. At block 308, the value X_{1 }is calculated by multiplying the values X_{0 }and R_{0}.
At decision block 310, it is determined if the operand type indicator OT indicates that the operands A and B are single precision values. If so, the method flow moves to block 312 and the quotient value Q_{i }is calculated by performing a rectangular multiplication of the values A and X_{1}. The method flow proceeds to block 314 and the value Q_{i }is rounded, based on the rounding control RC, to obtain the single precision floatingpoint quotient Q_{i}. To determine how the quotient will be rounded, a remainder REM is determined by performing a rectangular multiplication of the divisor B by the value Q_{i}, and subtracting the result from the dividend A. The remainder REM indicates if the value Q_{i }is greater than, less than, or equal to the true quotient Q. In an exemplary embodiment, in response to the rounding control indicator RC indicating the result Q_{f }should not be less than the quotient Q, the rounding ensures that the single precision result Q_{f }is greater than or equal to the quotient Q. In an alternative embodiment, in response to the rounding control indicator RC indicating the result Q_{f }should not be more than the quotient Q, the rounding can ensure that the single precision result Q_{f }is less than or equal to the quotient Q. At block 316, the rounded single precision quotient value Q_{f }is provided.
Returning to block 310, if the operand type indicator OT indicates that the operands are not single precision values, the method flow moves to decision block 318. At block 318, it is determined if the operand type indicator OT indicates that the operands are extended precision values and the precision control indicates that the quotient value should be a single precision value. If not, the method flow moves to block 320. At block 320, the value R_{1 }is calculated by reducing the value X_{1}, performing a rectangular multiplication of the divisor B and the reduced X_{1 }value, and determining a complement of the result. In a particular embodiment, the value X_{1 }is a 76 bit value and the reduced X_{1 }value is formed using bits 026 of the value X_{1}.
The method flow moves to block 322 and the value X_{2 }is calculated by performing a rectangular multiplication of the reduced X_{1 }value and the value R_{1}. The method flow proceeds to decision block 324, and it is determined whether the operand type indicator OT indicates that the operands are double precision values. If so, the method flow proceeds to block 326.
At block 326, the quotient value Q_{i }is calculated by performing a rectangular multiplication of the values A and X_{2}. The method flow proceeds to block 328 and the value Q_{i }is rounded, based on the rounding control RC, to obtain the single precision floatingpoint quotient Q_{f}. To determine how the quotient will be rounded, a remainder REM is determined by performing a rectangular multiplication of the divisor B by the value Q_{i}, and subtracting the result from the dividend A. The remainder REM indicates if the value Q_{i }is greater than, less than, or equal to the true quotient Q. The quotient value Q_{f }is provided at block 316.
Returning to block 324, if the operand type indicator OT indicates the operands are not double precision values, the method flow proceeds to block 332. In addition, at block 318 if the operand type indicator OT indicates the operands are extended precision values and the precision control indicates that the quotient should be a single precision value, the method flow moves to block 332.
At block 332, it is determined whether the precision control indicator PC indicates that the quotient should be a single precision value. If so, the method flow moves to block 346 and the quotient value Q_{i }is calculated by performing a rectangular multiplication of the value X_{1 }and a truncated value of the dividend A. In a particular embodiment, the dividend A is a 76 bit value, and the truncated A value is formed based on bits 026 of the value A.
The method flow proceeds to block 342 and the value Q_{i }is rounded, based on the rounding control RC, to obtain the single precision floatingpoint quotient Q_{f}. To determine how the quotient will be rounded, a remainder REM is determined by performing a rectangular multiplication of the divisor B by the value Q_{i}, and subtracting the result from the dividend A. The remainder REM indicates if the value Q_{i }is greater than, less than, or equal to the true quotient Q. The quotient value Q_{f }is provided at block 316.
If, at block 332, it is determined that the precision control indicator PC does not indicate that the quotient should be a single precision value, the method flow moves to decision block 334. At block 334, it is determined whether the precision control indicator PC indicates that the quotient should be a double precision value. If so, the method flow moves to block 346 and the quotient value Q_{i }is calculated by performing a rectangular multiplication of the value X_{2 }and the dividend A. The method flow proceeds to block 342, described previously.
If, at block 334, it is determined that the precision control indicator PC does not indicate that the quotient should be a double precision value, the method flow moves to block 336 and the value R_{2 }is calculated by reducing the value X_{2 }to determine a reduced X_{2 }value, performing a rectangular multiplication of the divisor value B and the reduced X_{2 }value determining a complement of the result. In a particular embodiment, the value X_{2 }is a 76 bit value and the reduced X_{2 }value is formed using bits 053 of the value X_{2}. The method flow moves to block 338 and the value X_{3 }is calculated by performing a rectangular multiplication of the values X_{2 }and R_{2}. The method flow proceeds to block 340 and the quotient value Q_{i }is calculated by performing a rectangular multiplication of the values A and X_{3}. The method flow proceeds to block 342, described previously.
Referring to
For each pass through the multiplier 430 the appropriate 27bits of the multiplier operand are selected by the Unpack/Align Multiplexers. Two sets of radix4 Booth encoders are required to support the dual 24bit by 24bit multiplication mode. The Booth multiplexers produce fourteen 81bit partial products which are compressed along with the two 76bit feedback terms using a partial product reduction tree implemented using 3 levels of 42 compressors. For the first pass the feedback terms are all zeros. For subsequent passes, the feedback terms are obtained from the upper 76bits of the carrysave product produced by the previous pass.
The rounding scheme implemented in the second stage 404 involves adding a rounding constant to the carrysave product using a 32 carrysave adder prior to the addition. The rounding is performed prior to normalization using two additions, with one addition assuming no overflow occurs and one addition assuming overflow occurs. A third addition computes the unrounded mantissa. Since for wider precision multiplies the product generation is split over multiple cycles, the lower 27bits are processed after each pass to compute sticky and the carryin for the next pass. The appropriate rounding constant is taken into account for the first two additions and is omitted for the unrounded mantissa, which requires two separate carry trees.