Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

• US 7,962,716 B2
• Filed: 11/17/2004
• Issued: 06/14/2011
• Est. Priority Date: 03/22/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L., Hogenauer, Eugene, Scheuermann, Walter James
• Primary Examiner(s): Chan, Eddie
• Assistant Examiner(s): Partridge, William B
• Application Number:
  US10/990,800
• Publication Number:
  US 20050091472A1
• Time in Patent Office: 2,400 Days
• Field of Search: 712/15, 712/29
• US Class Current: 712/11
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Claims

1. An adaptive computing engine comprising:

a first configurable unit to perform computational functions comprising a first plurality of computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the computational elements coupled to each other via a first interconnection network to configure interconnections between the computational elements in response to configuration information to perform a computational function; and

a second configurable unit for performing digital signal processing functions comprising a second plurality of computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements being heterogeneous and coupled to each other via a second interconnection network to configure the interconnections between the second plurality of computational elements in response to configuration information to perform a first digital signal processing function, the interconnections between the secondary plurality of computational elements being changeable to reconfigure the second plurality of computational elements in response to different configuration information to perform a second digital signal processing function, the second plurality of computational elements having at least one different type of computational element than those of the first plurality of computational elements.

2. The adaptive computing engine of claim 1, wherein the first configurable unit and the second configurable unit are organized in a computing matrix, and the computing matrix is coupled to a matrix interconnection network.

3. The adaptive computing engine of claim 2, wherein the matrix interconnection network is coupled to a plurality of computing matrices, each computing matrix having a plurality of computational units.

4. The adaptive computing engine of claim 1, wherein the first plurality of computational elements is organized as a computational architecture and the second plurality of computational elements is organized as a digital signal processing architecture.

5. The adaptive computing engine of claim 3, wherein a configured function of the computational matrix is a controller having a controller function.

6. The adaptive computing engine of claim 5, wherein the controller function includes sending configuration information via the matrix interconnection network to configure one of the plurality of configurable computing matrices.

7. The adaptive computing engine of claim 5, wherein the controller is a RISC controller.

8. The adaptive computing engine of claim 2, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

9. The adaptive computing engine of claim 2, wherein the matrix interconnection network transmits configuration information to the computing matrix to configure the computing matrix to perform the function.

10. The adaptive computing engine of claim 1, wherein the computational function includes one of a group of linear operation, memory, memory management, and bit level manipulation.

11. The adaptive computing engine of claim 1, wherein the first plurality of computational elements comprises different ones of a group of an adder and a function generator having data inputs and a control input to select a specific function.

12. The adaptive computing engine of claim 1, further comprising a third interconnection network coupled to the first configurable computational unit and the second configurable digital signal processing unit, the third interconnection network sending the configuration information to the configurable units.

13. The adaptive computing engine of claim 12, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

14. The adaptive computing engine of claim 1, wherein the first interconnection network includes multiplexers coupled to the first plurality of computational elements and the second interconnection network includes multiplexers coupled to the second plurality of computational elements.

15. The adaptive computing engine of claim 14, wherein the configuration information includes control signals to control the multiplexers.

16. The adaptive computing engine of claim 1, wherein the first interconnection network provides second configuration information to reconfigure the first configurable computational unit to perform a second computational function.

17. The adaptive computing engine of claim 1, wherein the second plurality of computational elements of the digital signal processing computational unit each perform a function from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.

18. The adaptive computing engine of claim 1, wherein the digital signal processing function is one of fixed point arithmetic functions, floating point arithmetic functions, filtering functions, and transformation functions.

39. The adaptive computing engine of claim 1, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

40. The adaptive computing engine of claim 1, wherein the first plurality of computational elements is heterogeneous and includes a function generator and an adder, the function generator having data inputs and a control input to select a specific function;

and

wherein the second plurality of computational elements includes a multiplier and an adder.

41. The adaptive computing engine of claim 40, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

42. The adaptive computing engine of claim 1, wherein the computational function includes a function generator and an adder, the function generator having data inputs and a control input to select a specific function;

and

wherein the digital signal processing function includes a multiplier and an adder.

43. The adaptive computing engine of claim 42, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

44. The adaptive computing engine of claim 18, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

45. The adaptive computing engine of claim 44, wherein the computational function includes a function generator and an adder, the function generator having data inputs and a control input to selection a specific function;

and

wherein the digital signal processing function includes a multiplier and an adder.

46. The adaptive computing engine of claim 1, wherein at least one computational element of the second plurality of computational elements is bypassed via the interconnections between the second plurality of computational elements.

47. The adaptive computing engine of claim 1, wherein the second plurality of computational elements has a different combination of computational elements including an identical type than the first plurality of computational elements including the identical type.

66. The adaptive computing engine of claim 1, wherein the first plurality of computational elements is heterogeneous.

19. An integrated circuit comprising:

a first configurable unit for performing computational functions comprising a first computational architecture formed from a first plurality of computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the computational elements coupled to each other via a first interconnection network to configure interconnections between the computational elements in response to configuration information to perform a computational function; and

a second configurable unit for performing digital signal processing functions comprising a second digital signal processing architecture formed from a second plurality of computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the computational elements coupled to each other via a second interconnection network to configure interconnections between the computational elements in response to configuration information to perform a digital signal processing function, the second plurality of computational elements having at least one different type of computational element than those of the first plurality of computational elements;

a third interconnection network coupled to the first configurable unit and the second configurable unit, the third interconnection network having switchable connections to the first and second configurable unit and in response to configuration information, wherein the first and second interconnection networks have denser interconnections to the computational elements than the interconnections of the third interconnection network to the computational units.

20. The integrated circuit of claim 19, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

21. The integrated circuit of claim 19, wherein the computational function includes one of a group of linear operation, memory, memory management, and bit level manipulation.

22. The integrated circuit of claim 19, wherein the first plurality of computational elements includes different ones of a group of an adder and a function generator having data inputs and a control input to select a specific function.

23. The integrated circuit of claim 19, wherein the first interconnection network includes multiplexers coupled to the first plurality of computational elements and the second interconnection network includes multiplexers coupled to the second plurality of computational elements.

24. The integrated circuit of claim 23, wherein the configuration information includes control signals to control the multiplexers.

25. The integrated circuit of claim 19, wherein the first interconnection network provides second configuration information to reconfigure the first configurable unit to perform a second computational function.

26. The integrated circuit of claim 19, wherein the second plurality of computational elements of the digital signal processing computational unit comprises at least two computational elements which each perform a function from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.

27. The integrated circuit of claim 19, wherein the digital signal processing function is one of fixed point arithmetic functions, floating point arithmetic functions, filtering functions, and transformation functions.

48. The integrated circuit of claim 19, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

49. The integrated circuit of claim 19, wherein the first plurality of computational elements is heterogeneous and includes a function generator and an adder;

and

wherein the second plurality of computational elements includes a multiplier and an adder.

50. The integrated circuit of claim 49, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

51. The integrated circuit of claim 19, wherein the basic computational function includes a function generator and an adder, the function generator having data inputs and a control input to selection a specific function;

and

wherein the digital signal processing function includes a multiplier and an adder.

52. The integrated circuit of claim 51, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

53. The integrated circuit of claim 27, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

54. The integrated circuit of claim 53, wherein the computational function includes a function generator and an adder, the function generator having data inputs and a control input to selection a specific function;

and

wherein the digital signal processing function includes a multiplier and an adder.

55. The integrated circuit of claim 19, wherein at least one of the second plurality of computational elements is bypassed via the interconnections between the second plurality of computational elements.

56. The integrated circuit of claim 19, wherein the second plurality of computational elements has a different combination of computational elements including an identical type than the first plurality of computational elements including the identical type.

28. An integrated circuit comprising:

a first configurable unit for performing computational functions comprising a first plurality of computational elements, at least two of which each perform an arithmetic operation and each having components in a fixed architecture with fixed connections between the components, the first plurality of computational elements each coupled to each other via a first interconnection network to configure interconnections between the computational elements in response to configuration information to perform a computational function; and

a second configurable unit for performing digital signal processing functions comprising a second plurality of computational elements, at least two of which each perform an arithmetic operation, the second plurality of computational elements being heterogeneous and each having components in a fixed architecture with fixed connections between the components, the second plurality of computational elements coupled to each other via a second interconnection network to configure interconnections between the computational elements in response to configuration information to perform a digital signal processing function, the second plurality of computational elements having a different combination of computational elements than the first plurality of computational elements.

29. The integrated circuit of claim 28, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

30. The integrated circuit of claim 28, wherein the computational function includes one of a group of linear operation, memory, memory management, and bit level manipulation.

31. The integrated circuit of claim 28, wherein the first plurality of computational elements comprises different ones of a group of an adder and a function generator having data inputs and a control input to select a specific function.

32. The integrated circuit of claim 28, further comprising a third interconnection network coupled to the first configurable computational unit and the second configurable unit, the third interconnection network sending the configuration information to the configurable units.

33. The integrated circuit of claim 32, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

34. The integrated circuit of claim 28, wherein the first interconnection network includes multiplexers coupled to the first plurality of computational elements and the second interconnection network includes multiplexers coupled to the second plurality of computational elements.

35. The integrated circuit of claim 34, wherein the configuration information includes control signals to control the multiplexers.

36. The integrated circuit of claim 28, wherein the first interconnection network provides second configuration information to reconfigure the first configurable unit to perform a second computational function.

37. The integrated circuit of claim 28, wherein the second plurality of computational elements of the digital signal processing computational unit comprises at least two computational elements which each perform a function from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.

38. The integrated circuit of claim 28, wherein the digital signal processing function is one of fixed point arithmetic functions, floating point arithmetic functions, filtering functions, and transformation functions.

57. The integrated circuit of claim 28, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

58. The integrated circuit of claim 28, wherein the first plurality of computational elements are heterogeneous and includes a function generator and an adder, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of computational elements includes a multiplier and an adder.

59. The integrated circuit of claim 58, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

60. The integrated circuit of claim 28, wherein the basic computational function includes a function generator and an adder, the function generator having data inputs and a control input to selection a specific function;

and

wherein the digital signal processing function includes a multiplier and an adder.

61. The integrated circuit of claim 60, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

62. The integrated circuit of claim 38, wherein the computational function comprises bit level manipulation;

and wherein the digital signal processing function comprises bit or word level manipulation.

63. The integrated circuit of claim 62, wherein the computational function includes a function generator and an adder, the function generator having data inputs and a control input to select a specific function;

and

wherein the digital signal processing function includes a multiplier and an adder.

64. The integrated circuit of claim 28, wherein one type of the second plurality of computational elements is bypassed via the interconnections between the second plurality of computational elements.

65. The integrated circuit of claim 28, wherein the second plurality of computational elements has at least one different type of computational element than those of the first plurality of computational elements.