System and method for preserving processor memory during power loss

• US 7,962,787 B2
• Filed: 01/29/2008
• Issued: 06/14/2011
• Est. Priority Date: 01/29/2008
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH, Robert Bosch LLC (Robert Bosch GmbH)
• Original Assignee: Robert Bosch GmbH
• Inventors: Camilleri, Paul M., Gohl, Jerry A.
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): Truong; Loan
• Application Number:
  US12/022,005
• Publication Number:
  US 20090193278A1
• Time in Patent Office: 1,232 Days
• Field of Search: 714/24, 714/14, 323/282
• US Class Current: 714/24
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A method, and a system of using the method, of preserving memory of a processor powered by an external source. The method includes determining a drop in a first power to be supplied to the processor, generating a reset signal when the drop falls below a threshold, supplying a second power from a power store to the processor based on the reset signal, and holding the reset signal until the first power rises above the threshold.

Claims

1. A method of preserving memory of a processor configured to be powered by an external source, the method comprising:

determining a drop in a first power to be supplied to the processor;

generating a first intermediate reset signal when the first power falls below a threshold;

supplying a second power from a store to the processor based on the first intermediate reset signal;

deriving a reference signal from the second power;

comparing the reference signal with the first power;

generating a second intermediate reset signal when the reference signal is greater than the first power;

activating a reset circuit with at least one of the first intermediate reset signal and the second intermediate reset signal; and

outputting a processor reset signal from the reset circuit.

2. The method of claim 1, wherein supplying a second power from a store comprises:

activating a switch when the first intermediate reset signal is activated; and

coupling the store to the processor.

3. The method of claim 1, wherein the store comprises a capacitor, the method further comprising charging the capacitor with a supply circuit.

4. The method of claim 1, further comprising deactivating the reset signal when the first power is above the threshold.

5. A circuit for preserving memory of a processor, the circuit comprising:

a voltage regulator configured to receive a first power from an external source, to provide power to the processor based on the first power, to determine a level of the first power supplied to the processor, and to generate a first intermediate reset signal when the level of the first power drops below a threshold;

a switch coupled to the voltage regulator, and configured to be activated based on the first intermediate reset signal, and to transfer a second power to the processor via the voltage regulator;

a reference supply configured to receive the second power and to derive a reference signal from the second power;

a comparator configured to generate a second intermediate reset signal when the level of the first power is below the reference signal; and

a reset circuit configured to receive the first intermediate reset signal and the second intermediate reset signal and to output a processor reset signal based on at least one of the first intermediate reset signal and the second intermediate reset signal.

6. The circuit of claim 5, further comprising a switch controller configured to receive the first intermediate reset signal and to activate the switch.

7. The circuit of claim 5, further comprising a capacitor configured to store the second power and to deliver the second power to the processor.

8. The circuit of claim 7, further comprising a supply circuit configured to charge the capacitor.

9. A method of preserving memory of a processor, the method comprising:

supplying a first power to the processor from a power supply;

storing at least a portion of the first power from the power supply in a store;

determining a drop in the first power to be supplied to the processor;

generating a first intermediate reset signal when the first power falls below a threshold;

coupling the store to the processor when the first intermediate reset signal is active;

supplying a second power from the store to the processor;

deriving a reference signal from the second power;

comparing the reference signal with the first power;

generating a second intermediate reset signal when the reference signal is greater than the first power;

activating a reset circuit based on at least one of the first intermediate reset signal and the second intermediate reset signal;

outputting a processor reset signal from the reset circuit; and

holding the reset signal until the first power rises above the threshold.

10. The method of claim 9, wherein supplying a second power from the store comprises:

activating a switch when the processor reset signal is activated; and

coupling the store to the processor.

11. The method of claim 9 further comprising charging a capacitor with a supply circuit.

12. The method of claim 9, further comprising deactivating the reset signal when the first power is above the threshold.

13. A circuit for preserving an output of a processor, the circuit comprising:

a voltage regulator configured to receive a first power from an external source, to provide power to the processor based on the first power, to determine a level of the first power supplied to the processor, and to generate a first intermediate reset signal when the level of the first power drops below a threshold;

a store configured to store auxiliary power;

a switch configured to couple the store to the voltage regulator when the first intermediate reset signal is activated, and to transfer a second power from the store to the processor via the voltage regulator;

a reference supply configured to receive the second power and to derive a reference signal from the second power;

a comparator configured to generate a second intermediate reset signal when the level of the first power is below the reference signal; and

a reset circuit configured to receive the first intermediate reset signal and the second intermediate reset signal and to output a processor reset signal based on at least one of the first intermediate reset signal and the second intermediate reset signal.

14. The circuit of claim 13, further comprising a switch controller configured to receive the first intermediate reset signal and to activate the switch.

15. The circuit of claim 13, wherein the store comprises a capacitor configured to store the auxiliary power and to deliver the auxiliary power to the processor.

16. The circuit of claim 15, further comprising a supply circuit configured to charge the capacitor.