Fault diagnosis of compressed test responses

• US 7,962,820 B2
• Filed: 03/17/2009
• Issued: 06/14/2011
• Est. Priority Date: 02/13/2003
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Wang, Chen, Mrugalski, Grzegorz, Tyszer, Jerzy, Pogiel, Artur, Rajski, Janusz
• Primary Examiner(s): Gaffin; Jeffrey A
• Assistant Examiner(s): Gandhi; Dipakkumar
• Application Number:
  US12/405,828
• Publication Number:
  US 20090249147A1
• Time in Patent Office: 819 Days
• Field of Search: None
• US Class Current: 714/732
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

Claims

1. One or more computer-readable storage devices storing computer-executable instructions which when executed by a computer cause the computer to perform a method the method comprising:

receiving at least one error signature comprising multiple bits, the bits of the error signature comprising one or more error bits that indicate errors in a compressed test response produced by a compactor in a circuit-under-test;

evaluating plural potential-error-bit-explaining scan cell candidates using a search tree; and

determining whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells.

2. The one or more computer-readable storage devices of claim 1, wherein the method further comprises selecting the error signature from a list of error signatures, the selection being based at least partially on the number of errors in the error signature.

3. The one or more computer-readable storage devices of claim 1, wherein the act of receiving at least one error signature comprises receiving an error signature corresponding to a compressed test response for a single applied test pattern.

4. The one or more computer-readable storage devices of claim 1, wherein the act of receiving at least one error signature comprises receiving an error signature corresponding to the initial compressed test response for one or more applied test patterns.

5. The one or more computer-readable storage devices of claim 1, wherein the method further comprises prioritizing the order in which the scan cell candidates are evaluated using the search tree, the order being at least partially dependent on one or more of (a) whether the respective scan cell candidates were previously determined to be failing scan cells, (b) whether the respective scan cell candidates are in a scan chain having one or more scan cells that were previously determined to be failing scan cells, (c) the number of error bits in the error signature that are determined in part by scan cells output during the same time period as the respective scan cell candidates, (d) whether the error signature received matches a generic error pattern indicative of two or more errors masking one another in the compactor, or (e) weights assigned to the scan cell candidates, the weights corresponding to a likelihood that a respective scan cell candidate is at least a part of a solution group of one or more failing scan cells that explains the error bits in the one or more error signature.

6. The one or more computer-readable storage devices of claim 1, wherein the act of receiving at least one error signature comprises receiving at least first and second error signatures, and wherein the act of determining further comprises determining whether the one or more failing scan cells determined to explain the error bits in the first error signature also explain error bits of the second error signature, the second error signature being different from the first error signature.

7. The one or more computer-readable storage devices of claim 1, wherein the act of receiving at least one error signature further comprises receiving at least one error signature with one or more unknown bits that indicate unknown values at corresponding bit locations of the compressed test response.

8. The one or more computer-readable storage devices of claim 1, wherein the method further comprises storing a list of the one or more failing scan cells and using the list to locate a defect in the circuit-under-test.

9. One or more computer-readable storage devices storing computer-executable instructions which when executed by a computer cause the computer to perform a method the method comprising:

receiving an error signature comprising multiple bits, the bits of the error signature comprising one or more error bits that indicate errors in a compressed test response produced by a compactor in a circuit-under-test;

selecting at least one error bit of the error signature;

selecting at least one scan cell candidate from a set of scan cells known to contribute to the bit of the compressed test response corresponding to the selected at least one error bit; and

determining whether the selected at least one scan cell candidate explains the selected at least one error bit in the error signature by updating the error signature to include the contribution of the at least one selected error bit.

10. The one or more computer-readable storage devices of claim 9, wherein the act of determining further comprises, if the selected at least one scan cell candidate does not explain the selected at least one error bit in the error signature, using the updated error signature as the error signature and iteratively repeating the method at least one time.

11. The one or more computer-readable storage devices of claim 10, wherein the method further comprises backtracking to an earlier iteration if no solution is found, the solution being one or more scan cells that explain the presence of the selected at least one error bit of one error signature.

12. The one or more computer-readable storage devices of claim 10, wherein the method further comprises backtracking to an earlier iteration if progress toward a solution does not meet a threshold after a predetermined number of scan cell candidates have been selected and determined not to explain the selected at least one error bit.

13. The one or more computer-readable storage devices of claim 9, wherein the act of updating the error signature is performed by computing a bit-wise modulo-two sum of the error signature and an error print associated with the selected at least one scan cell candidate.

14. The one or more computer-readable storage devices of claim 9, wherein the method further comprises diagnosing a defect in the circuit-under-test using one or more scan cells determined to explain the presence of the selected at least one error bit of one error signature.

15. A system for diagnosing faults in a circuit-under-test, comprising:

means for receiving at least one error signature comprising multiple bits, the bits of the error signature comprising one or more error bits that indicate errors in a compressed test response;

means for evaluating plural potential-error-bit-explaining scan cell candidates using a search tree; and

means for determining whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells.

16. The system of claim 15, further comprising means for selecting the error signature from a list of error signatures, the selection being based at least partially on the number of errors in the error signature.

17. The system of claim 15, wherein the means for receiving at least one error signature comprises means for receiving an error signature corresponding to a compressed test response for a single applied test pattern.

18. The system of claim 15, further comprising means for prioritizing the order in which the scan cell candidates are evaluated using the search tree, the order being at least partially dependent on one or more of (a) whether the respective scan cell candidates were previously determined to be failing scan cells, (b) whether the respective scan cell candidates are in a scan chain having one or more scan cells that were previously determined to be failing scan cells, (c) the number of error bits in the error signature that are determined in part by scan cells output during the same time period as the respective scan cell candidates, (d) whether the error signature received matches a generic error pattern indicative of two or more errors masking one another in the compactor, or (e) weights assigned to the scan cell candidates, the weights corresponding to a likelihood that a respective scan cell candidate is at least a part of a solution group of one or more failing scan cells that explains the error bits in the one or more error signature.

19. The system of claim 15, wherein the means for receiving at least one error signature comprises means for receiving at least first and second error signatures, and wherein the act of determining further comprises determining whether the one or more failing scan cells determined to explain the error bits in the first error signature also explain error bits of the second error signature, the second error signature being different from the first error signature.

20. The system of claim 15, wherein the means for receiving at least one error signature further comprises means for receiving at least one error signature with one or more unknown bits that indicate unknown values at corresponding bit locations of the compressed test response.