Unified memory architecture for recording applications

• US 7,962,833 B2
• Filed: 10/12/2009
• Issued: 06/14/2011
• Est. Priority Date: 12/12/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Qian, Cheng, Juluri, Rajesh
• Primary Examiner(s): Torres; Joseph D
• Application Number:
  US12/577,382
• Publication Number:
  US 20100031123A1
• Time in Patent Office: 610 Days
• Field of Search: 714/769, 714/785, 714/755, 714/756
• US Class Current: 714/769
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11B 2020/10787 parameters, e.g. for decoding or encoding
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes

Abstract

An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.

Claims

1. An apparatus comprising:

a first circuit that (i) generates an input signal by reading compressed-and-encoded video from a source, (ii) extracts video data as a first block arranged as a Reed-Solomon product code from said input signal, (iii) transfers said first block onto a first bus, (iv) calculates a plurality of correction values in final form corresponding to said first block while said first block remains unaltered as initially written in an external memory, (v) retrieves said first block from said first bus and (vi) corrects said first block as received via said first bus with said correction values to generate corrected video data; and

a second circuit that (i) decodes said corrected video data to generate decoded video data while in a first state, (ii) encodes said decoded video data to generated encoded video data in a second internal signal while in a second state, (iii) receives said first block from said first circuit via said first bus, (iv) transfers said first block to said external memory via a second bus, (v) receives said first block from said external memory via said second bus and (vi) transfers said first block to said first circuit via said first bus.

2. The apparatus according to claim 1, wherein said first circuit comprises an error correction code module that generates (i) a plurality of syndromes from said first block and (ii) said correction values from said syndromes.

3. The apparatus according to claim 2, wherein said error correction code module comprises a row syndrome module that calculates a plurality of first row syndromes of said syndromes from said first block.

4. The apparatus according to claim 3, wherein said error correction code module further comprises a column syndrome module that calculates a plurality of first column syndromes of said syndromes from said first block.

5. The apparatus according to claim 4, wherein said error correction code module further comprises a decoder module that decodes in a sequence alternating between a first pass and a second pass, wherein (i) said first pass comprises decoding said first column syndromes to generate column correction results and (ii) said second pass comprises decoding said first row syndromes to generate row correction results.

6. The apparatus according to claim 5, wherein said error correction code module further comprises a delta syndrome module that (i) updates said first row syndromes in response to said column correction results and (ii) updates said first column syndromes in response to said row correction results.

7. The apparatus according to claim 6, further comprising a local memory coupled to said row syndrome module, said column syndrome module, said delta syndrome module and said decoder module, wherein said local memory (i) stores both said first row syndromes and said first column syndromes from said first block while said syndromes are being updated, (ii) stores said correction values in place of said syndromes once updating is complete and (iii) excludes said first block.

8. The apparatus according to claim 7, wherein said first circuit further comprising a buffer connected to said first bus, wherein said buffer (i) stores at least two rows of said first block and (ii) presents said first block one row at a time to both said first bus and said column syndrome module.

9. The apparatus according to claim 8, wherein said external memory stores said first block as presented from said buffer.

10. The apparatus according to claim 7, wherein said local memory stores both a plurality of second row syndromes and a plurality of second column syndromes from a second block of said input signal substantially simultaneously with storing said first row syndromes and said first column syndromes of said first block.

11. The apparatus according to claim 10, wherein said row syndrome module writes said second row syndromes of said second block substantially simultaneously with said delta syndrome module updating said first row syndromes and said first column syndromes of said first block.

12. The apparatus according to claim 7, further comprising a dispatcher module connected between said local memory and said decoder module, wherein said dispatcher module presents a plurality of decode jobs from said local memory to said decode module based on a corresponding priority of said decode jobs.

13. The apparatus according to claim 12, wherein each of said decode jobs comprises one of (i) decoding said first row syndromes and (ii) decoding said first column syndromes.

14. The apparatus according to claim 6, wherein said decoder module further generates said correction values based on said syndromes.

15. The apparatus according to claim 1, wherein said first bus implements a stream data interface.

16. The apparatus according to claim 1, wherein said second bus implements an AT attachment packet interface that is controlled by said second circuit.

17. The apparatus according to claim 1, wherein a bandwidth of said first bus is at least three times a data rate of said first block.

18. The apparatus according to claim 1, wherein said transfer of said first block from said second circuit to said first circuit is performed only after all calculations of said correction values have completed.

19. The apparatus according to claim 1, wherein said second circuit uses said external memory while in said first state and said second state.

20. An apparatus comprising:

means for (i) generating an input signal by reading compressed-and-encoded video from a source, (ii) extracting video data as a first block arranged as a Reed-Solomon product code from said input signal, (iii) transferring said first block to onto a first bus, (iv) calculating a plurality of correction values in final form corresponding to said first block while said first block remains unaltered as initially written in an external memory, (v) retrieving said first block from said first bus and (vi) correcting said first block as received via said first bus with said correction values to generate corrected video data; and

means for (i) decoding said corrected video data to generated decoded video data while in a first state, (ii) encoding said decoded video data to generated encoded video data in a second internal signal while in a second state, (iii) receiving said first block from said first bus, (iv) transferring said first block to said external memory via a second bus, (v) receiving said first block from said external memory via said second bus and (vi) transferring said first block to said means for retrieving via said first bus.