Stage yield prediction

• US 7,962,864 B2
• Filed: 05/22/2008
• Issued: 06/14/2011
• Est. Priority Date: 05/24/2007
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Nehmadi, Youval, Schwarm, Alexander T., Shimshi, Rinat, Svidenko, Vicky, Jawaharlal, Sundar
• Primary Examiner(s): WHITMORE, STACY
• Application Number:
  US12/154,458
• Publication Number:
  US 20080295047A1
• Time in Patent Office: 1,118 Days
• Field of Search: 716 50- 55, 700/121
• US Class Current: 716/51
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

In one embodiment, a method for predicting yield during the design stage includes receiving defectivity data identifying defects associated with previous wafer designs, and dividing the defects into systematic defects and random defects. For each design layout of a new wafer design, yield is predicted separately for the systematic defects and the random defects. A combined yield is then calculated based on the yield predicted for the systematic defects and the yield predicted for the random defects.

Claims

1. A computer-implemented method comprising:

storing defectivity data identifying one or more defects associated with one or more previous wafer designs in memory, wherein the defectivity data comprises data gathered from inspections performed on wafers having the previous wafer designs;

dividing the defects associated with one or more design elements of the previous wafer designs into systematic defects and random defects;

for each design layout of a new wafer design, predicting a yield separately for systematic defects and random defects associated with the new wafer design using the defectivity data associated with the previous wafer designs, wherein the new wafer design has no inspection and metrology data gathered; and

calculating a combined yield based on the yield predicted for the systematic defects and the yield predicted for the random defects.

2. The computer-implemented method of claim 1, wherein predicting the yield for systematic defects comprises:

applying, for each design layout of a new design, systematic defects from the one or more previous designs to the new design layout;

associating each of systematic defects of the one or more previous designs with a calculated yield impact;

applying the yield impact to the design elements of the new design layout,

determining a yield loss for each of the design elements using the yield impacts, and

combining the yield losses to determine a total yield loss for the new design layout.

3. The computer-implemented method of claim 2, wherein applying systematic defects from the one or more previous designs to the new design layout comprises:

identifying systematic defects in one or more previous designs;

searching the new design layout for the identified systematic defects; and

applying a failure rate associated with the identified systematic defects to the new design layout.

4. The computer-implemented method of claim 1, wherein predicting the yield for random defects of the new design layout comprises for each critical layer:

applying random defect distribution information for each design element in the one or more previous designs corresponding to the design elements in the new design;

performing a simulation using the defect distribution information applied to the new design layouts to generate, for each design element, virtual defects on the new design;

calculating a CF value for the virtual defects, using geometric characteristics of the virtual defects;

applying the CF values of the virtual defects to yield correlation curves imported from previous designs, wherein the yield correlation curves correlate yield impact to the CF values; and

combining the yield impact of each of the virtual defects.

5. The computer-implemented method of claim 4, wherein the random defect distribution information is received from at least one of:

an inspection and metrology data database, and a design data database.

6. The computer-implemented method of claim 4, wherein the simulation is a Monte Carlo simulation.

7. The computer-implemented method of claim 1, wherein the systematic defect information and the random defect information is stored in at least one of:

a design data database, and an inspection and metrology data database.

8. A computer-implemented system comprising:

memory to store design data for previous wafer designs and new wafer designs, wherein the design data comprises at least one of;

wafer design layouts, and routing information for the wafer design layouts;

memory to store defectivity information associated with the previous wafer designs, wherein the defectivity data comprises data gathered from inspections performed on wafers having the previous wafer designs; and

a design-stage yield analyzer, coupled to the memory to identify a new wafer design, wherein the new wafer design has no inspection and metrology data gathered, to identify defects on the new wafer design using the defectivity information associated with the previous wafer designs, and to predict yield for each wafer design layout for the new wafer design.

9. The computer-implemented system of claim 8, wherein the defect information associated with previous designs include at least one of:

a size of the defects, a volume of the defects, and a location of the defects within the previous designs.

10. The computer-implemented system of claim 8, further comprising a report generator to generate a report specifying an optimal design layout for a new design.

11. The computer-implemented system of claim 8, wherein the design stage yield-analyzer comprises:

a design element identifier to divide previous layouts into design elements and to determine a design/defect interaction for a design element, wherein the design/defect interaction in relation to specify defects likely to occur for a specific design element;

a criticality factor calculator to calculate a criticality factor (CF) of individual defects; and

a yield predictor to predict yield for each new design layout using the design/defect interaction associated with the design elements.

12. The computer-implemented system of claim 11, wherein the design elements are to be defined by at least one of:

a line density and a component density.

13. The computer-implemented system of claim 11, wherein the design element identifier further comprises a pattern density calculator to calculate a pattern density of the design elements using geometric characteristics of the defects and design data obtained from the design data database.

14. The computer-implemented system of claim 11, wherein the design element identifier is to receive at least one of:

pattern density, and design/defect interaction information for previous designs from at least one of;

an inspection and metrology data database, and a pattern density reporter.

15. The computer-implemented system of claim 11, wherein the yield predictor predicts yield for each new design layout by:

dividing the defects into systematic defects and random defects;

for each design layout of a new design, predicting yield separately for the systematic defects and the random defects; and

calculating a combined yield based on the yield predicted for the systematic defects and the yield predicted for the random defects.

16. The computer-implemented system of claim 15, wherein the yield predictor is to predict yield for random defects based on the criticality factor (CF) of individual defects calculated by the CF calculator.

17. The computer-implemented system of claim 16, wherein the CF calculator is to calculate a criticality factor (CF) of individual defects based on a size or a volume of the defect, and the layout of the design element on which the defect is found.

18. A computer-implemented apparatus comprising:

means for storing defectivity data identifying one or more defects associated with one or more previous wafer designs, wherein the defectivity data comprises data gathered from inspections performed on wafers having the previous wafer designs;

means for dividing the defects associated with one or more design elements of the previous wafer designs into systematic defects and random defects;

for each design layout of a new wafer design, means for predicting a yield separately for systematic defects and random defects associated with the new wafer design using the defectivity data associated with the previous wafer designs, wherein the new wafer design has no inspection and metrology data gathered; and

means for calculating a combined yield based on the yield predicted for the systematic defects and the yield predicted for the random defects.

19. A non-transitory computer readable storage medium, comprising executable instructions which when executed on a processing system cause the processing system to perform a method comprising:

storing defectivity data identifying one or more defects associated with one or more previous wafer designs in memory, wherein the defectivity data comprises data gathered from inspections performed on wafers having the previous wafer designs;

dividing the defects associated with one or more design elements of the previous wafer designs into systematic defects and random defects;

for each design layout of a new wafer design, predicting a yield separately for systematic defects and random defects associated with the new wafer design using the defectivity data associated with the previous wafer designs, wherein the new wafer design has no inspection and metrology data gathered; and

calculating a combined yield based on the yield predicted for the systematic defects and the yield predicted for the random defects.

20. The non-transitory computer readable storage medium of claim 19, wherein predicting the yield for systematic defects comprises:

applying, for each design layout of a new design, systematic defects from the one or more previous designs to the new design layout;

associating each of systematic defects of the one or more previous designs with a calculated yield impact;

applying the yield impact to the design elements of the new design layout,

determining a yield loss for each of the design elements using the yield impacts, and

combining the yield losses to determine a total yield loss for the new design layout.

21. The non-transitory computer readable storage medium of claim 19, wherein predicting the yield for random defects of the new design layout comprises for each critical layer:

applying random defect distribution information for each design element in the one or more previous designs corresponding to the design elements in the new design;

performing a simulation using the defect distribution information applied to the new design layouts to generate, for each design element, virtual defects on the new design;

calculating a CF value for the virtual defects, using geometric characteristics of the virtual defects;

applying the CF values of the virtual defects to yield correlation curves imported from previous designs, wherein the yield correlation curves correlate yield impact to the CF values; and

combining the yield impact of each of the virtual defects.