Electronic design for integrated circuits based on process related variations

• US 7,962,867 B2
• Filed: 01/28/2008
• Issued: 06/14/2011
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Smith, Taber H., White, David
• Primary Examiner(s): Dinh; Paul
• Application Number:
  US12/021,298
• Publication Number:
  US 20080216027A1
• Time in Patent Office: 1,233 Days
• Field of Search: 716 51- 56, 716110-114, 716/119, 716/132, 716/136
• US Class Current: 716/54
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]

Abstract

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

Claims

1. A computer-implemented method for predicting a characteristic of an integrated circuit, comprising:

using at least one processor that is programmed for performing a process, the process comprising;

using a pattern-dependent model of a fabrication process to predict a variation of a characteristic of an integrated circuit that is to be fabricated in accordance with a design by the fabrication process, wherein

the variation is predicted based at least in part upon an analysis of an interaction between the fabrication process and a second fabrication process for the integrated circuit, and

the fabrication process and the second fabrication process for the integrated circuit are both used to fabricate the integrated circuit; and

determining a placement attribute and a routing attribute for an element of the integrated circuit based at least in part on the variation of the characteristic that is predicted to improve performance or manufacturing of the integrated circuit, wherein

the element comprises one or more buffer regions for one or more components in the pattern dependent model,

the element comprises one or more dummy fills or one or more slotting structures for the design of the integrated circuit, and

the action of determining the placement attribute and the routing attribute comprises determining whether the variation exceeds a focus limit.

2. The method of claim 1, in which the placement or the routing attribute comprises one or more attributes of buffer regions for interconnect vias and lines determined during a placement or a routing step in the design.

3. The method of claim 1, in which the characteristic predicted comprises a width variation or a topographical variation, and the placement or the routing attribute comprises a placement location of an electrically active feature or component.

4. The method of claim 1, in which the characteristic predicted comprises a width variation or a geographical variation, and the placement or the routing attribute comprises a routing of an interconnect feature across the integrated circuit.

5. The method of claim 1, in which the characteristic predicted comprises placement of a dummy fill or a slotting structure.

6. The method of claim 1, in which the characteristic predicted comprises a geometry of a dummy fill or a slotting structure.

7. The computer-implemented method of claim 1, wherein the analysis of the interaction between the fabrication process and the second fabrication process for the integrated circuit comprises an electrical impact analysis that is used by the act of using the pattern-dependent model of the fabrication process to predict the variation of the characteristic of the integrated circuit.

8. The computer-implemented method of claim 1, wherein the fabrication process or the second fabrication process comprises a high-density plasma process, a planarization process, a patterning process, an electroplated copper deposition, a dielectric film generation process, a material removal process, or a photoresist generation or removal process for fabrication of the integrated circuit.

9. A system for predicting a characteristic of an integrated circuit, comprising:

at least one processor that is programmed for performing a process, the process comprising;

using a pattern-dependent model of a fabrication process to predict a variation of a characteristic of an integrated circuit that is to be fabricated in accordance with a design by the fabrication process, wherein

the variation is predicted based at least in part upon an analysis of an interaction between the fabrication process and a second fabrication process for the integrated circuit, and

the fabrication process and the second fabrication process for the integrated circuit are both used to fabricate the integrated circuit; and

determining a placement attribute and a routing attribute for an element of the integrated circuit based at least in part on the characteristic that is predicted to improve performance or manufacturing of the integrated circuit, wherein

the element comprises one or more buffer regions for one or more components in the pattern dependent model,

the element comprises one or more dummy fills or one or more slotting structures for the design of the integrated circuit, and

the action of determining the placement attribute and the routing attribute comprises determining whether the variation exceeds a focus limit.

10. The system of claim 9, in which the placement or the routing attribute comprises one or more attributes of buffer regions for interconnect vias and lines determined during a place and route step in the design.

11. The system of claim 9, in which the characteristic predicted comprises a width variation or a topographical variation, and the placement or the routing attribute comprises a placement location of an electrically active feature or component.

12. The system of claim 9, in which the characteristic predicted comprises a width variation or a geographical variation, and the placement or the routing attribute comprises a routing of an interconnect feature across the integrated circuit.

13. The system of claim 9, in which the characteristic predicted comprises placement of a dummy or a slotting structure.

14. The system of claim 9, in which the characteristic predicted comprises a geometry of a dummy or a slotting structure.

15. The system of claim 9, wherein the analysis of the interaction between the fabrication process and the second fabrication process for the integrated circuit comprises an electrical impact analysis that is used by the act of using the pattern-dependent model of the fabrication process to predict the variation of the characteristic of the integrated circuit.

16. A computer program product comprising a non-transitory tangible computer-usable storage medium having executable code which, when executed by at least one processor, causes the at least one processor to execute a method for predicting a characteristic of an integrated circuit, the method comprising:

using the at least one processor that is programmed for performing a process, the process comprising;

using a pattern-dependent model of a fabrication process to predict a variation of a characteristic of an integrated circuit that is to be fabricated in accordance with a design by the fabrication process, wherein

the variation is predicted based at least in part upon an analysis of an interaction between the fabrication process and a second fabrication process for the integrated circuit, and

the fabrication process and the second fabrication process for the integrated circuit are both used to fabricate the integrated circuit; and

determining a placement attribute and a routing attribute for an element of the integrated circuit based at least in part on the variation of the characteristic that is predicted to improve performance or manufacturing of the integrated circuit, wherein

the element comprises one or more buffer regions for one or more components in the pattern dependent model,

the element comprises one or more dummy fills or one or more slotting structures for the design of the integrated circuit, and

the action of determining the placement attribute and the routing attribute comprises determining whether the variation exceeds a focus limit.

17. The computer program product of claim 16, in which the placement or the routing attribute comprises one or more attributes of buffer regions for interconnect vias and lines determined during a place and route step in the design.

18. The computer program product of claim 16, in which the characteristic predicted comprises a width variation or a topographical variation, and the placement or the routing attribute comprises a placement location of an electrically active feature or component.

19. The computer program product of claim 16, in which the characteristic predicted comprises a width variation or a geographical variation, and the placement or the routing attribute comprises a routing of an interconnect feature across the integrated circuit.

20. The computer program product of claim 16, in which the characteristic predicted comprises placement of a dummy or a slotting structure.

21. The computer program product of claim 16, in which the characteristic predicted comprises a geometry of a dummy or a slotting structure.

22. The computer program product of claim 16, wherein the analysis of the interaction between the fabrication process and the second fabrication process for the integrated circuit comprises an electrical impact analysis that is used by the act of using the pattern-dependent model of the fabrication process to predict the variation of the characteristic of the integrated circuit.