Wafer processing apparatus with wafer alignment device
First Claim
Patent Images
1. A semiconductor-processing apparatus comprising:
- a wafer handling chamber;
at least one wafer processing chamber, each connected to the wafer handling chamber;
a wafer handling device disposed in the wafer handling chamber for loading a wafer in the wafer processing chamber, said wafer handling device comprising an end effector for placing a wafer thereon, said end effector being movable from a ready-to-load position to the wafer processing chamber in an x-axis direction which is a wafer loading direction and in a y-axis which is perpendicular to the x-axis direction on a wafer loading plane;
at least one first photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer placed on the end effector partially blocks light received by the first photosensor at the ready-to-load position and entirely blocks light received by the first photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction; and
at least one second photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer placed on the end effector does not block light received by the second photosensor at the ready-to-load position and partially blocks but never entirely blocks light received by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction,wherein the first photosensor is adapted to output a first analogue signal indicative of quantity of light sensed by the first photosensor at the ready-to-load position, and the second photosensor is adapted to output a second analogue signal indicative of lowest quantity of light sensed by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber,wherein the first and second photosensors are disposed at positions such that an amount of a wafer deviation, a, in the x-axis direction is determinable by the equation
a=a′
+(R−
√
{square root over ((R2−
b2))})wherein a′
is an amount of a wafer deviation detected by the first photosensor, b is an amount of a wafer deviation detected by the second photosensor, and R is a radius of the wafer.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor-processing apparatus includes: a wafer handling chamber; a wafer processing chamber; a wafer handling device; a first photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer partially blocks light received by the first photosensor at a ready-to-load position and substantially entirely blocks light received by the first photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction; and a second photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer does not block light received by the second photosensor at the ready-to-load position and partially blocks light received by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction.
461 Citations
16 Claims
-
1. A semiconductor-processing apparatus comprising:
-
a wafer handling chamber; at least one wafer processing chamber, each connected to the wafer handling chamber; a wafer handling device disposed in the wafer handling chamber for loading a wafer in the wafer processing chamber, said wafer handling device comprising an end effector for placing a wafer thereon, said end effector being movable from a ready-to-load position to the wafer processing chamber in an x-axis direction which is a wafer loading direction and in a y-axis which is perpendicular to the x-axis direction on a wafer loading plane; at least one first photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer placed on the end effector partially blocks light received by the first photosensor at the ready-to-load position and entirely blocks light received by the first photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction; and at least one second photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer placed on the end effector does not block light received by the second photosensor at the ready-to-load position and partially blocks but never entirely blocks light received by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction, wherein the first photosensor is adapted to output a first analogue signal indicative of quantity of light sensed by the first photosensor at the ready-to-load position, and the second photosensor is adapted to output a second analogue signal indicative of lowest quantity of light sensed by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber, wherein the first and second photosensors are disposed at positions such that an amount of a wafer deviation, a, in the x-axis direction is determinable by the equation
a=a′
+(R−
√
{square root over ((R2−
b2))})wherein a′
is an amount of a wafer deviation detected by the first photosensor, b is an amount of a wafer deviation detected by the second photosensor, and R is a radius of the wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeASM Japan K.K. (ASM International NV)
-
Original AssigneeASM Japan K.K. (ASM International NV)
-
InventorsAkagawa, Masayuki, Suwada, Masaei, Takizawa, Masahiro
-
Primary Examiner(s)Lowe; Michael S
-
Application NumberUS12/062,419Publication NumberTime in Patent Office1,174 DaysField of Search414/217, 414/935, 414/936US Class Current414/217CPC Class CodesH01L 21/681 using optical controlling m...H01L 21/68707 the wafers being placed on ...Y10S 414/135 Associated with semiconduct...Y10S 414/136 including wafer orienting m...
