Schemes for forming barrier layers for copper in interconnect structures

• US 7,964,496 B2
• Filed: 11/21/2006
• Issued: 06/21/2011
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Bao, Tien-I, Chen, Hai-Ching
• Primary Examiner(s): Sarkar; Asok K
• Application Number:
  US11/602,808
• Publication Number:
  US 20080119047A1
• Time in Patent Office: 1,673 Days
• Field of Search: 257/E21.199, 257/E21.584, 438/627, 438/630, 438/643, 438/664, 438/687
• US Class Current: 438/627
• CPC Class Codes: H01L 21/322 to modify their internal properties, e.g. to produce internal imperfections
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Claims

1. A method of forming a semiconductor structure, the method comprising:

providing a substrate;

forming a low-k dielectric layer over the substrate;

embedding a conductive wiring in the low-k dielectric layer; and

thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring, wherein the thermal soaking occurs in a non-plasma environment, the barrier layer comprising a silicide.

2. The method of claim 1, wherein the conductive wiring comprises copper.

3. The method of claim 1, wherein the step of thermal soaking is performed with plasma turned off.

4. The method of claim 1, wherein the step of thermal soaking is performed at a temperature of between about 150°

C. and about 450°

C.

5. The method of claim 1, wherein the carbon-containing silane-based chemical comprises a material selected from the group consisting essentially of SiH₃(CH₃)₁ (1MS), SiH₂(CH₃)₂ (2MS), and combinations thereof.

6. The method of claim 5, wherein the carbon-containing silane-based chemical is free from Si(CH₃)₄ (4MS).

7. The method of claim 1, wherein the step of embedding the conductive wiring comprises:

forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer; and

forming a lining barrier layer lining the opening, wherein the lining barrier layer comprises a metal selected from the group consisting essentially of cobalt, nickel, and combinations thereof, and wherein during the step of thermal soaking, the metal reacts with the carbon-containing silane-based chemical to form silicide on top edges of the lining barrier layer.

8. The method of claim 1 further comprising performing a treatment to a surface of the barrier layer using C_xH_y.

9. A method of forming a semiconductor structure, the method comprising:

providing a substrate;

forming a low-k dielectric layer over the substrate;

forming an opening extending from a top surface of the low-k dielectric layer into the low-k dielectric layer;

forming a first barrier layer lining the opening, wherein the first barrier layer comprises a metal selected from the group consisting essentially of cobalt, nickel, and combinations thereof;

embedding a conductive wiring in a remaining portion of the opening; and

thermal soaking a top surface of the conductive wiring in a silane-based chemical comprising SiH₃(CH₃)₁ (1MS), SiH₂(CH₃)₂ (2MS), and combinations thereof to form a silicide second barrier layer on the conductive wiring and top edges of the first barrier layer.

10. The method of claim 9 further comprising performing a treatment to a top surface of the silicide second barrier layer using C_xH_y.