Strained silicon on relaxed sige film with uniform misfit dislocation density

• US 7,964,865 B2
• Filed: 02/03/2005
• Issued: 06/21/2011
• Est. Priority Date: 09/23/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Dokumaci, Omer H., Chidambarrao, Dureseti
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): Kraig; William F
• Application Number:
  US11/048,739
• Publication Number:
  US 20050164477A1
• Time in Patent Office: 2,329 Days
• Field of Search: 257/18, 257/19, 257/E21.123, 257/E29.298, 257/E29.193, 438/478
• US Class Current: 257/19
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.

Claims

1. A semiconductor device comprising:

a silicon substrate;

a relaxed SiGe layer formed on the silicon substrate, said SiGe layer including uniformly distributed misfit dislocations at an interface between the silicon substrate and the relaxed SiGe layer; and

a tensilely strained silicon layer formed on the relaxed SiGe layer.

2. The semiconductor device of claim 1, wherein the density of the misfit dislocations in the SiGe layer is approximately 1×

10⁵ loops/cm² to 1×

10¹² loops/cm².

3. The semiconductor device of claim 1, wherein the misfit dislocations are arranged in a shape of grid when viewed from above.

4. The semiconductor device of claim 1, wherein the SiGe layer is formed at a thickness of approximately 100 Å

to 10000 Å

.

5. The semiconductor device of claim 1, wherein the density of misfit dislocations in the SiGe layer, measured at an interface between the silicon substrate and the SiGe layer, is approximately 1×

10⁵ loops/cm² to 1×

10¹² loops/cm².

6. The semiconductor device of claim 5, wherein the density of misfit dislocations in the SiGe layer is approximately 1×

10⁵ loops/cm² to 1×

10¹² loops/cm².