Semiconductor device having a protective circuit

• US 7,964,874 B2
• Filed: 05/19/2008
• Issued: 06/21/2011
• Est. Priority Date: 04/15/2002
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Murakami, Satoshi, Fujikawa, Saishi, Hirosue, Takashi, Osame, Mitsuaki, Hayakawa, Masahiko, Kato, Kiyoshi, Yamazaki, Shunpei
• Primary Examiner(s): Soward; Ida M
• Application Number:
  US12/122,823
• Publication Number:
  US 20080230871A1
• Time in Patent Office: 1,128 Days
• Field of Search: 257/40, 257/68, 257/71, 257/E27.024, 257/E27.025, 257/E27.033, 257/E27.034, 257/E27.044, 257/E27.045, 257/E27.048, 257/E27.071, 257/E27.117
• US Class Current: 257/71
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 85/1135 Polyethylene dioxythiophene [PEDOT]; Derivatives thereof
• CPC Class Codes: Y10S 257/906 Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

Claims

1. A semiconductor device having a protective circuit, the protective circuit comprising:

a first capacitor electrode formed over a substrate;

a first inorganic insulating film formed over the first capacitor electrode;

an organic resin film formed over the first inorganic insulating film;

an opening formed in the organic resin film;

a second inorganic insulating film formed over the organic resin film and in contact with the first inorganic insulating film in the opening; and

a second capacitor electrode formed over the second inorganic insulating film,

wherein the radius of curvature on a surface of the organic resin film is continuously lengthened as the distance from the opening is increased.

2. A semiconductor device comprising:

an input terminal;

a protective circuit formed over a substrate, the protective circuit comprising;

a capacitor including;

(a) a first electrode electrically connected to the input terminal;

(b) a first inorganic insulating film formed over the first electrode;

(c) a photosensitive organic resin film formed over the first inorganic insulating film;

(d) an opening formed in the organic resin film;

(e) a second inorganic insulating film formed over the organic resin film and

in contact with the first inorganic insulating film in the opening; and

(f) a second electrode electrically connected to a voltage supply line, the second electrode being formed over the second inorganic insulating film wherein the second electrode overlaps with the first electrode in the opening with the first inorganic insulating film and the second inorganic insulating film interposed therebetween; and

a thin film transistor electrically connected to the input terminal and the voltage supply line;

a lead wiring electrically connected to the input terminal through the protective circuit; and

a circuit electrically connected to the input terminal through the lead wiring.

3. The semiconductor device according to claim 2 wherein a surface of the opening of the organic resin film is rounded.

4. The semiconductor device according to claim 2 wherein the semiconductor device is a display device.