Display device

• US 7,964,876 B2
• Filed: 01/27/2010
• Issued: 06/21/2011
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi
• Primary Examiner(s): Dickey; Thomas L
• Application Number:
  US12/694,514
• Publication Number:
  US 20100133533A1
• Time in Patent Office: 510 Days
• Field of Search: 257/59, 257/72, 349/44
• US Class Current: 257/72
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/023 using energy recovery or conservation
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01H 71/02 Housings; Casings; Bases; Mountings
• CPC Class Codes: H01H 71/10 Operating or release mechanisms
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 : with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 : with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 : comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/13 : combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/42384 : for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78663 : Amorphous silicon transistors
• CPC Class Codes: H01L 29/78678 : with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals

Abstract

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a circuit configured to apply an AC pulse to a gate electrode of the second transistor;

a clock wiring;

a power supply line; and

an output node,

wherein the first transistor and the second transistor are connected in series between the clock wiring and the power supply line,

wherein the first transistor and the second transistor are connected to the output node, and

wherein a semiconductor layer including a channel formation region of each of the first transistor and the second transistor comprises an oxide semiconductor.

2. The semiconductor device according to claim 1, wherein a capacitor is provided between an electrode of the first transistor and the gate electrode of the first transistor.

3. The semiconductor device according to claim 1, wherein each of the first transistor and the second transistor is an n-channel transistor.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor is one of ZnO, a-InGaZnO, IZO, ITO, and SnO.

5. An electronic device comprising the semiconductor device according to claim 1.

6. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a first clock wiring;

a second clock wiring;

a first power supply line;

a second power supply line; and

an output node,

wherein the first transistor and the second transistor are connected in series between the first clock wiring and the first power supply line,

wherein a first electrode of the third transistor is connected to a gate electrode of the second transistor, a second electrode of the third transistor is connected to the second clock wiring, and a gate electrode of the third transistor is connected to the second power supply line,

wherein the first transistor and the second transistor are connected to the output node, and

wherein a semiconductor layer including a channel formation region of each of the first to third transistors comprises an oxide semiconductor.

7. The semiconductor device according to claim 6, wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the greatest among values of ratios W/L of the first to third transistors.

8. The semiconductor device according to claim 6, wherein a capacitor is provided between the second electrode of the first transistor and the gate electrode of the first transistor.

9. The semiconductor device according to claim 6, wherein each of the first to third transistors is an n-channel transistor.

10. The semiconductor device according to claim 6, wherein the oxide semiconductor is one of ZnO, a-InGaZnO, IZO, ITO, and SnO.

11. An electronic device comprising the semiconductor device according to claim 6.

12. A display device comprising:

a pixel portion including a plurality of pixels; and

a driver circuit electrically connected to the pixel portion,

wherein the driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,

wherein a first electrode of the first transistor is electrically connected to a fourth wiring, and a second electrode of the first transistor is electrically connected to a third wiring,

wherein a first electrode of the second transistor is electrically connected to a sixth wiring, and a second electrode of the second transistor is electrically connected to the third wiring,

wherein a first electrode of the third transistor is electrically connected to a fifth wiring, a second electrode of the third transistor is electrically connected to a gate electrode of the second transistor, and a gate electrode of the third transistor is electrically connected to a seventh wiring,

wherein a first electrode of the fourth transistor is electrically connected to the sixth wiring, a second electrode of the fourth transistor is electrically connected to the gate electrode of the second transistor, and a gate electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor,

wherein a first electrode of the fifth transistor is electrically connected to the seventh wiring, a second electrode of the fifth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the fifth transistor is electrically connected to a first wiring,

wherein a first electrode of the sixth transistor is electrically connected to the sixth wiring, a second electrode of the sixth transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the sixth transistor is electrically connected to the gate electrode of the second transistor, and

wherein a first electrode of the seventh transistor is electrically connected to the sixth wiring, a second electrode of the seventh transistor is electrically connected to the gate electrode of the first transistor, and a gate electrode of the seventh transistor is electrically connected to a second wiring, and

wherein a semiconductor layer including a channel formation region of each of the first to seventh transistors comprises an oxide semiconductor.

13. The display device according to claim 12, wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the greatest among values of ratios W/L of the first to seventh transistors.

14. The display device according to claim 12, wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is two to five times greater than a value of a ratio W/L of the fifth transistor.

15. The display device according to claim 12, wherein a channel length L of the third transistor is larger than a channel length L of the fourth transistor.

16. The display device according to claim 12, wherein a capacitor is provided between the second electrode of the first transistor and the gate electrode of the first transistor.

17. The display device according to claim 12, wherein each of the first to seventh transistors is an n-channel transistor.

18. The display device according to claim 12, wherein the oxide semiconductor is one of ZnO, a-InGaZnO, IZO, ITO, and SnO.

19. The display device according to claim 12, wherein the driver circuit is a flip-flop circuit.

20. An electronic device comprising the display device according to claim 12.