Power MOS transistor incorporating fixed charges that balance the charge in the drift region

• US 7,964,913 B2
• Filed: 01/08/2008
• Issued: 06/21/2011
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): Louie; Wai-Sing
• Assistant Examiner(s): Jahan; Bilkis
• Application Number:
  US11/971,139
• Publication Number:
  US 20080164518A1
• Time in Patent Office: 1,260 Days
• Field of Search: 257/331, 257/330, 257/329, 257/334, 257/E29.262
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/2003 characterised by the substrate
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Claims

1. A semiconductor device comprising:

a plurality of trenches penetrating into semiconductor material, wherein

at least some ones of said trenches include a gate electrode which is capacitively coupled to a portion of said semiconductor material to control conduction therethrough, and

at least some ones of said trenches have fixed electrostatic charge of at least 5×

10¹¹ cm<sup>−

2</sup> in proximity to sidewalls thereof;

and wherein said fixed electrostatic charge balances at least some of the net charge in depleted regions of said semiconductor material, when said semiconductor material is depleted.

2. The semiconductor device of claim 1, wherein said gate electrode consists of a doped polycrystalline semiconductor material.

3. The semiconductor device of claim 1, wherein at least some ones of said trenches which have fixed charge in proximity thereto contain a dielectric material.

4. The semiconductor device of claim 1, wherein at least some ones of said trenches have said fixed electrostatic charge in proximity to sidewalls thereof, but do not include any gate electrode.

5. The semiconductor device of claim 1, wherein at least some ones of said trenches include a gate electrode and also include said fixed electrostatic charge in proximity to sidewalls thereof.

6. The semiconductor device of claim 1, wherein an integrated doping density, measured from one of said trenches which has said fixed electrostatic charge to a neighboring trench which has fixed charge ranges from about 1×

10¹² cm<sup>−

2</sup> to about 5×

10¹² cm<sup>−

2</sup>.

7. The semiconductor device of claim 1, wherein said trenches which have said fixed electrostatic charge in proximity to sidewalls thereof contain aluminum oxide.

8. The semiconductor device of claim 1, wherein said gate electrode controls conduction, through said semiconductor material, between heavily doped semiconductor source and drain regions.

9. The semiconductor device of claim 1, wherein said trenches which have said fixed electrostatic charge in proximity to sidewalls thereof include at least two different dielectric materials.

10. The semiconductor device of claim 1, wherein said trenches which have said fixed electrostatic charge in proximity to sidewalls thereof include aluminum fluoride.

11. The semiconductor device of claim 1, wherein said trenches which have said fixed electrostatic charge in proximity to sidewalls thereof contain silicon dioxide.

12. The semiconductor device of claim 1, further comprising, in addition to said trenches, one or more termination trenches.

13. A semiconductor device comprising:

a first-conductivity-type source overlying at least some portions of a second-conductivity-type body layer;

first trenches, each including at least one conductive gate electrode which is capacitively coupled to a portion of said body, to thereby control passage of majority carriers emitted by said source through portions of said body, and optionally through a drift region, to a drain;

a plurality of second trenches, interspersed with said first trenches; and

fixed electrostatic charge of at least 5×

10¹¹ cm<sup>−

2</sup> in proximity to sidewalls of said second trenches;

wherein said fixed electrostatic charge balances at least some of the net charge in depleted regions of said body and/or drift region, when a depletion boundary spreads from the junction between said body and said drain.

14. The semiconductor device of claim 13, wherein said gate electrode consists of a doped polycrystalline semiconductor material.

15. The semiconductor device of claim 13, wherein said second trenches include at least two different dielectric materials.

16. The semiconductor device of claim 13, further comprising, in addition to said first and second trenches, one or more termination trenches.

17. The semiconductor device of claim 13, wherein said first and second trenches are both implemented by a single type of trench, each of which includes both said gate electrode and also, in proximity to sidewalls thereof, said fixed electrostatic charge.

18. A semiconductor device comprising:

semiconductor material in which a source region at least partly overlies a body region;

a plurality of trenches extending down into said semiconductor material;

at least some ones of said trenches including at least one conductive gate electrode which is capacitively coupled to a respective portion of said body diffusion to control conduction therethrough; and

fixed electrostatic charge of at least 5×

10¹¹ cm<sup>−

2</sup>, in proximity to sidewalls of ones of said trenches;

wherein said fixed electrostatic charge balances at least some of the net charge in depleted regions of said semiconductor material, when said semiconductor material is depleted.

19. The semiconductor device of claim 18, wherein said gate electrode consists of a doped polycrystalline semiconductor material.

20. The semiconductor device of claim 18, wherein at least some ones of said trenches which have fixed charge in proximity thereto contain a dielectric material.

21. The semiconductor device of claim 18, wherein at least some ones of said trenches have said fixed electrostatic charge in proximity to sidewalls thereof, but do not include any gate electrode.

22. The semiconductor device of claim 18, wherein at least some ones of said trenches include a gate electrode and also include said fixed electrostatic charge in proximity to sidewalls thereof.