Method for fabrication of a semiconductor device and structure

• US 7,964,916 B2
• Filed: 06/02/2010
• Issued: 06/21/2011
• Est. Priority Date: 04/14/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Beinglass, Israel, Cronquist, Brian, Sekar, Deepak C., Or-Bach, Zvi, de Jong, Jan L.
• Primary Examiner(s): Tran; Tan N
• Application Number:
  US12/792,673
• Publication Number:
  US 20100295136A1
• Time in Patent Office: 384 Days
• Field of Search: 257/67, 257/69, 257/347, 257/353, 257/E21.193
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H03K 19/177 : arranged in matrix form
• CPC Class Codes: H03K 19/17704 : the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element

Abstract

A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Claims

1. A semiconductor device comprising:

a first single crystal silicon layer comprising a plurality of first transistors and a plurality of first alignment marks;

at least two metal layers overlying said first single crystal silicon layer,

wherein said metal layers comprise copper or aluminum more than other materials,

wherein said metal layers provide connections between said first transistors, wherein said metal layers comprise a third metal layer overlying a second metal layer that overlies a first metal layer, and wherein said third metal layer and said first metal layer each has an associated pitch that is tighter than a pitch associated with said second metal layer; and

a second thin single crystal silicon layer of less than 0.4 micron thickness overlying said metal layers, wherein said second thin single crystal silicon layer comprises a plurality of second planar transistors, wherein said second planar transistors are aligned with said first alignment marks.

2. A semiconductor device according to claim 1, wherein said second thin single crystal silicon layer is constructed by a layer transfer process.

3. A semiconductor device according to claim 1, wherein said plurality of second planar transistors are annealed by an optical annealing.

4. A semiconductor device according to claim 1, wherein said second planar transistors are source extension transistors.

5. A semiconductor device comprising:

a first single crystal silicon layer comprising a plurality of first transistors and a plurality of first alignment marks;

at least two metal layers overlying said first single crystal silicon layer, wherein said metal layers comprise copper or aluminum more than other materials, wherein said metal layers provide connections between said first transistors; and

a second thin single crystal silicon layer of less than 0.4 micron thickness overlying said metal layers, wherein said second thin single crystal silicon layer comprises a plurality of second planar transistors, wherein said second thin single crystal silicon layer further comprises a second alignment mark, and wherein said plurality of second planar transistors are aligned with said first alignment marks by an offset, wherein said offset relates to a distance between one of said first alignment marks and said second alignment mark.

6. A semiconductor device according to claim 5, wherein said second thin single crystal silicon layer is constructed by a layer transfer process.

7. A semiconductor device according to claim 5, wherein said plurality of second planar transistors are annealed by an optical annealing.

8. A semiconductor device according to claim 5, wherein said second planar transistors are source extension transistors.