Chip structure
First Claim
1. A semiconductor chip comprising:
- a silicon substrate;
a transistor in or on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metal layer over said silicon substrate and over said first dielectric layer;
a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer;
a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer;
a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point; and
a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, and a gold layer over said second electroplated copper layer, wherein said gold layer has a thickness between 1 and 10 micrometers, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer.
4 Assignments
0 Petitions
Accused Products
Abstract
A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.
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Citations
64 Claims
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1. A semiconductor chip comprising:
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a silicon substrate; a transistor in or on said silicon substrate; a first dielectric layer over said silicon substrate; a first metal layer over said silicon substrate and over said first dielectric layer; a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer; a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer; a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point; and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, and a gold layer over said second electroplated copper layer, wherein said gold layer has a thickness between 1 and 10 micrometers, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit component comprising:
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a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer, a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer, a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point, and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer and a gold layer over said second electroplated copper layer, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer; and a glass substrate connected to said fourth metal layer of said semiconductor chip. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A circuit component comprising:
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a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer, a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer, a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point, and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, a nickel layer on said second electroplated copper layer, and a gold layer on said nickel layer; and a glass substrate connected to said fourth metal layer of said semiconductor chip. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A circuit component comprising:
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a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer, a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer, a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point, and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer and a gold layer over said second electroplated copper layer, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer; and a flexible substrate connected to said fourth metal layer of said semiconductor chip. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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30. A semiconductor chip comprising:
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a silicon substrate; a transistor in or on said silicon substrate; a first dielectric layer over said silicon substrate; a metallization structure over said silicon substrate and over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer; a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises an insulating nitride layer having a thickness between 0.2 and 1.2 micrometers; a metal trace on said separating layer, wherein there is no polymer layer between said metal trace and said separating layer, wherein said metal trace comprises a third metal layer on said separating layer and a first electroplated copper layer having a thickness between 2 and 30 micrometers on said third metal layer and over said separating layer; a first metal bump on said metal trace, wherein said first metal bump comprises a fourth metal layer on said metal trace and a second electroplated copper layer having a thickness between 7 and 30 micrometers on said fourth metal layer; and a second metal bump on said metal trace, wherein said second metal bump is connected to said first metal bump through said metal trace. - View Dependent Claims (31, 32)
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33. A semiconductor chip comprising:
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a silicon substrate; a transistor in or on said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a passivation layer over said silicon substrate, said metallization structure and said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer; a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 and 50 micrometers; and a metal bump connected to said first contact point through said first opening, wherein said metal bump comprises a copper layer and a gold-containing layer over said copper layer, wherein said metal bump has no portion vertically over said polymer layer, wherein said metal bump has a top surface at a first horizontal level higher than a second horizontal level of a top surface of said polymer layer, wherein said metal bump has a portion at a same horizontal level as said polymer layer, wherein said metal bump is spaced apart from said polymer layer. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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49. A semiconductor chip comprising:
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a silicon substrate; a transistor in or on said silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a dielectric layer between said first and second metal layers; a passivation layer over said silicon substrate, said metallization structure and said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer; a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 and 50 micrometers; and a metal bump connected to said first contact point through said first opening, wherein said metal bump comprises a copper layer having a thickness greater than 5 micrometers, wherein said metal bump has no portion vertically over said polymer layer, wherein said metal bump has a top surface at a first horizontal level higher than a second horizontal level of a top surface of said polymer layer, wherein said metal bump has a portion at a same horizontal level as said polymer layer, wherein said metal bump is spaced apart from said polymer layer. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64)
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Specification