Chip structure

• US 7,964,973 B2
• Filed: 09/01/2008
• Issued: 06/21/2011
• Est. Priority Date: 08/12/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chou, Chiu-Ming, Lin, Mou-Shiung, Chou, Chien-Kang, Lo, Hsin-Jung
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US12/202,342
• Publication Number:
  US 20090108453A1
• Time in Patent Office: 1,023 Days
• Field of Search: 257738-739, 257774-786
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05673 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05676 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.

Claims

1. A semiconductor chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a first metal layer over said silicon substrate and over said first dielectric layer;

a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer;

a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer;

a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point; and

a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, and a gold layer over said second electroplated copper layer, wherein said gold layer has a thickness between 1 and 10 micrometers, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer.

2. The semiconductor chip of claim 1, wherein said first metal layer comprises electroplated copper.

3. The semiconductor chip of claim 1, wherein said passivation layer comprises a nitride layer with a thickness between 0.2 and 1.2 micrometers.

4. The semiconductor chip of claim 1, wherein said passivation layer comprises a topmost nitride layer of said semiconductor chip.

5. The semiconductor chip of claim 1, wherein said third metal layer further comprises a titanium-containing layer over said passivation layer, on said first contact point and under said first electroplated copper layer.

6. The semiconductor chip of claim 1, wherein said fourth metal layer further comprises a nickel layer between said second electroplated copper layer and said gold layer.

7. The semiconductor chip of claim 1 further comprising a polymer layer on said passivation layer, wherein said third metal layer is further on said polymer layer.

8. The semiconductor chip of claim 1, wherein a second opening in said passivation layer is over a second contact point of said second metal layer, and said second contact point is at a bottom of said second opening in said passivation layer, wherein said third metal layer is further on said second contact point, wherein said first contact point is connected to said second contact point through said third metal layer.

9. A circuit component comprising:

a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer, a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer, a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point, and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer and a gold layer over said second electroplated copper layer, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer; and

a glass substrate connected to said fourth metal layer of said semiconductor chip.

10. The circuit component of claim 9, wherein said first metal layer comprises electroplated copper.

11. The circuit component of claim 9, wherein said passivation layer comprises a nitride layer with a thickness between 0.2 and 1.2 micrometers.

12. The circuit component of claim 9, wherein said third metal layer further comprises a titanium-containing layer over said passivation layer, on said first contact point and under said first electroplated copper layer.

13. The circuit component of claim 9, wherein said semiconductor chip further comprises a polymer layer on said passivation layer, wherein said third metal layer is further on said polymer layer.

14. The circuit component of claim 9, wherein a second opening in said passivation layer is over a second contact point of said second metal layer, and said second contact point is at a bottom of said second opening in said passivation layer, wherein said third metal layer is further on said second contact point, wherein said first contact point is connected to said second contact point through said third metal layer.

15. The circuit component of claim 9 further comprising multiple metal particles, in an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP), connecting said glass substrate to said fourth metal layer of said semiconductor chip.

16. A circuit component comprising:

a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer, a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer, a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point, and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer, a nickel layer on said second electroplated copper layer, and a gold layer on said nickel layer; and

a glass substrate connected to said fourth metal layer of said semiconductor chip.

17. The circuit component of claim 16, wherein said first metal layer comprises electroplated copper.

18. The circuit component of claim 16, wherein said passivation layer comprises a nitride layer with a thickness between 0.2 and 1.2 micrometers.

19. The circuit component of claim 16, wherein said third metal layer further comprises a titanium-containing layer over said passivation layer, on said first contact point and under said first electroplated copper layer.

20. The circuit component of claim 16, wherein said semiconductor chip further comprises a polymer layer on said passivation layer, wherein said third metal layer is further on said polymer layer.

21. The circuit component of claim 16, wherein a second opening in said passivation layer is over a second contact point of said second metal layer, and said second contact point is at a bottom of said second opening in said passivation layer, wherein said third metal layer is further on said second contact point, wherein said first contact point is connected to said second contact point through said third metal layer.

22. The circuit component of claim 16 further comprising multiple metal particles, in an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP), connecting said glass substrate to said fourth metal layer of said semiconductor chip.

23. A circuit component comprising:

a semiconductor chip comprising a silicon substrate, a transistor in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and over said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer, a passivation layer on said second metal layer, over said first metal layer and over said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said second metal layer, and said first contact point is at a bottom of said first opening in said passivation layer, a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a first electroplated copper layer having a thickness between 2 and 30 micrometers over said passivation layer and over said first contact point, and a fourth metal layer on said third metal layer, wherein said fourth metal layer comprises a second electroplated copper layer directly on said first electroplated copper layer and a gold layer over said second electroplated copper layer, wherein said gold layer is connected to said first electroplated copper layer through said second electroplated copper layer; and

a flexible substrate connected to said fourth metal layer of said semiconductor chip.

24. The circuit component of claim 23, wherein said first metal layer comprises electroplated copper.

25. The circuit component of claim 23, wherein said passivation layer comprises a nitride layer with a thickness between 0.2 and 1.2 micrometers.

26. The circuit component of claim 23, wherein said third metal layer further comprises a titanium-containing layer over said passivation layer, on said first contact point and under said first electroplated copper layer.

27. The circuit component of claim 23, wherein said semiconductor chip further comprises a polymer layer on said passivation layer, wherein said third metal layer is further on said polymer layer.

28. The circuit component of claim 23, wherein a second opening in said passivation layer is over a second contact point of said second metal layer, and said second contact point is at a bottom of said second opening in said passivation layer, wherein said third metal layer is further on said second contact point, wherein said first contact point is connected to said second contact point through said third metal layer.

29. The circuit component of claim 23 further comprising a solder connecting said flexible substrate to said fourth metal layer of said semiconductor chip.

30. A semiconductor chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said silicon substrate and over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer;

a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises an insulating nitride layer having a thickness between 0.2 and 1.2 micrometers;

a metal trace on said separating layer, wherein there is no polymer layer between said metal trace and said separating layer, wherein said metal trace comprises a third metal layer on said separating layer and a first electroplated copper layer having a thickness between 2 and 30 micrometers on said third metal layer and over said separating layer;

a first metal bump on said metal trace, wherein said first metal bump comprises a fourth metal layer on said metal trace and a second electroplated copper layer having a thickness between 7 and 30 micrometers on said fourth metal layer; and

a second metal bump on said metal trace, wherein said second metal bump is connected to said first metal bump through said metal trace.

31. The semiconductor chip of claim 30, wherein said third metal layer comprises titanium.

32. The semiconductor chip of claim 30, wherein said insulating nitride layer comprises silicon nitride.

33. A semiconductor chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said silicon substrate, said metallization structure and said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer;

a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 and 50 micrometers; and

a metal bump connected to said first contact point through said first opening, wherein said metal bump comprises a copper layer and a gold-containing layer over said copper layer, wherein said metal bump has no portion vertically over said polymer layer, wherein said metal bump has a top surface at a first horizontal level higher than a second horizontal level of a top surface of said polymer layer, wherein said metal bump has a portion at a same horizontal level as said polymer layer, wherein said metal bump is spaced apart from said polymer layer.

34. The semiconductor chip of claim 33, wherein said metal bump further comprises a titanium-containing layer between said copper layer and said first contact point.

35. The semiconductor chip of claim 33, wherein said passivation layer further comprises an oxide layer under said nitride layer.

36. The semiconductor chip of claim 33 further comprising a metal trace over said passivation layer, wherein said polymer layer is further on said metal trace.

37. The semiconductor chip of claim 33 further comprising a metal trace over said passivation layer, wherein said polymer layer is further on said metal trace, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said metal trace is connected to said second contact point through said second opening.

38. The semiconductor chip of claim 37, wherein said metal bump is connected to said metal trace.

39. The semiconductor chip of claim 33 further comprising a metal trace over said passivation layer, wherein said polymer layer is further on said metal trace, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, and wherein a third opening in said passivation layer is over a third contact point of said metallization structure, and said third contact point is at a bottom of said third opening, wherein said second contact point is connected to said third contact point through said metal trace.

40. The semiconductor chip of claim 33, wherein said metal bump further comprises a nickel-containing layer on said copper layer, wherein said gold-containing layer is further on said nickel-containing layer.

41. The semiconductor chip of claim 33, wherein said metal bump is configured to be connected to a solder on a circuit substrate.

42. The semiconductor chip of claim 41, wherein said solder is preformed on said circuit substrate.

43. The semiconductor chip of claim 33, wherein said first metal layer comprises electroplated copper.

44. The semiconductor chip of claim 33, wherein said second metal layer comprises aluminum.

45. The semiconductor chip of claim 33, wherein said nitride layer comprises silicon nitride.

46. The semiconductor chip of claim 33, wherein said polymer layer comprises polyimide.

47. The semiconductor chip of claim 33, wherein said metal bump is directly on said first contact point.

48. The semiconductor chip of claim 33, wherein said metal bump is directly on said first contact point and a top surface of said passivation layer.

49. A semiconductor chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said silicon substrate, said metallization structure and said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride layer;

a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 and 50 micrometers; and

a metal bump connected to said first contact point through said first opening, wherein said metal bump comprises a copper layer having a thickness greater than 5 micrometers, wherein said metal bump has no portion vertically over said polymer layer, wherein said metal bump has a top surface at a first horizontal level higher than a second horizontal level of a top surface of said polymer layer, wherein said metal bump has a portion at a same horizontal level as said polymer layer, wherein said metal bump is spaced apart from said polymer layer.

50. The semiconductor chip of claim 49, wherein said metal bump further comprises a titanium-containing layer between said copper layer and said first contact point.

51. The semiconductor chip of claim 49, wherein said passivation layer further comprises an oxide layer under said nitride layer.

52. The semiconductor chip of claim 49 further comprising a metal trace over said passivation layer, wherein said polymer layer is further on said metal trace.

53. The semiconductor chip of claim 49 further comprising a metal trace over said passivation layer, wherein said polymer layer is further on said metal trace, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said metal trace is connected to said second contact point through said second opening.

54. The semiconductor chip of claim 53, wherein said metal bump is connected to said metal trace.

55. The semiconductor chip of claim 49 further comprising a metal trace over said passivation layer, wherein said polymer layer is further on said metal trace, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, and wherein a third opening in said passivation layer is over a third contact point of said metallization structure, and said third contact point is at a bottom of said third opening, wherein said second contact point is connected to said third contact point through said metal trace.

56. The semiconductor chip of claim 49, wherein said metal bump is configured to be connected to a solder on a circuit substrate.

57. The semiconductor chip of claim 56, wherein said solder is preformed on said circuit substrate.

58. The semiconductor chip of claim 49, wherein said first metal layer comprises electroplated copper.

59. The semiconductor chip of claim 49, wherein said second metal layer comprises aluminum.

60. The semiconductor chip of claim 49, wherein said nitride layer comprises silicon nitride.

61. The semiconductor chip of claim 49, wherein said polymer layer comprises polyimide.

62. The semiconductor chip of claim 49, wherein said metal bump is directly on said first contact point.

63. The semiconductor chip of claim 49, wherein said metal bump is directly on said first contact point and a top surface of said passivation layer.

64. The semiconductor chip of claim 49, wherein said thickness of said copper layer is between 7 and 30 micrometers.