Synchronous page-mode phase-change memory with ECC and RAM cache

• US 7,965,546 B2
• Filed: 10/15/2009
• Issued: 06/21/2011
• Est. Priority Date: 04/26/2007
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Yu, Frank I-Kang, Lee, Charles C., Chow, David Q.
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US12/579,695
• Publication Number:
  US 20100027329A1
• Time in Patent Office: 614 Days
• Field of Search: 365/163, 365/238.5, 365/200
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0071 Write using write potential applied to access device gate
• CPC Class Codes: G11C 2013/0085 Write a page or sector of information simultaneously, e.g. a complete row or word line
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell'"'"'s set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

Claims

1. A method for writing to a phase-change memory comprising:

receiving from a host a burst write command including a host address and host data in a command buffer;

comparing a portion of the host address to a plurality of tags in a lookup table and for storing the host data in the lookup table when a tag in the plurality of tags matches the portion of the host address;

when the portion of the host address does not match any valid tag in the plurality of tags, allocating a new entry in the lookup table for the host address and storing the host data in the new entry;

copying the host data from the lookup table to the phase-change memory by storing a data word data as binary bits each represented by a chalcogenide glass layer having a melting point that is higher than a crystallization point, the chalcogenide glass layer forming a variable resistor that alters a sensing current when a binary bit is read; and

representing a first binary logic state using a crystalline state of the variable resistor and representing a second binary logic state using an amorphous state of the variable resistor for binary bits stored in the phase-change memory.

2. The method for writing to the phase-change memory of claim 1 wherein copying the host data from the lookup table to the phase-change memory comprises first transferring the host data from the lookup table to a multi-line page buffer, and then transferring the host data from the multi-line page buffer to the phase-change memory;

whereby host write data is stored in the lookup table before writing to the phase-change memory.

3. The method for writing to the phase-change memory of claim 1 further comprising:

applying a set current for a set period of time to selected cells in the phase-change memory to set variable resistors into the crystalline state when the binary bits being written are in the first binary logic state; and

applying a reset current for a reset period of time to the selected cells in the phase-change memory to reset variable resistors into the amorphous state when the binary bits being written are in the second binary logic state.

4. The method for writing to the phase-change memory of claim 3 wherein the reset current is at least twice the set current, and wherein the set current is at least twice a sensing current that passes through the variable resistor during a read operation;

wherein the set period of time is at least double the reset period of time,

whereby the variable resistor is set by a lower current for a longer time period, and reset by a higher current and a shorter time period.

5. The method for writing to the phase-change memory of claim 4 wherein the set period of time is about 100 nanoseconds.

6. The method for writing to the phase-change memory of claim 1 further comprising:

generating error-correction code for host data stored in the lookup table; and

checking and correcting errors in data read from the phase-change memory and stored in the lookup table using error-correction code stored in the phase-change memory,

whereby error correction is performed for data in the lookup table.

7. The method for writing to the phase-change memory of claim 1 further comprising:

retaining data words stored in the phase-change memory when power is disconnected,

wherein the alloy resistors remain in the amorphous state and remain in the crystalline state when power is disconnected;

whereby the data is stored in non-volatile memory.

8. The method for writing to the phase-change memory of claim 1 wherein the lookup table is a volatile memory, wherein lines of data words in the lookup table are lost when power is disconnected, while data words stored in the phase-change memory are retained when power is disconnected,

whereby data is stored in non-volatile memory and cached in volatile memory.

9. The method for writing to the phase-change memory of claim 1 wherein the lookup table comprises a smaller array of the memory cells each having the alloy resistor, the alloy resistor storing binary data as solid phases each having a different resistivity,

whereby the lookup table is non-volatile.