Multi-level cell access buffer with dual function

• US 7,965,550 B2
• Filed: 07/08/2009
• Issued: 06/21/2011
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Pyeon, Hong Beom
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/499,577
• Publication Number:
  US 20090273973A1
• Time in Patent Office: 713 Days
• Field of Search: 327/202, 327/208
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement

Abstract

An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.

Claims

1. A dual-mode circuit comprising:

a latch circuit having a first input and a second input, the latch circuit comprising a driving inverter having the second input;

the dual-mode circuit having a first mode of operation in which a first signal received at the first input is latched by the latch circuit;

the dual-mode circuit having a second mode of operation in which a second signal received at the second input is inverted by the driving inverter.

2. The dual-mode circuit of claim 1 further comprising a circuit for:

enabling the first input while in the first mode of operation;

disabling the second input while in the first mode of operation;

disabling the first input while in the second mode of operation;

enabling the second input while in the second mode of operation.

3. The dual-mode circuit of claim 2 wherein the circuit for enabling the first input while in the first mode of operation, disabling the second input while in the first mode of operation, disabling the first input while in the second mode of operation, and enabling the second input while in the second mode of operation comprises:

a first pass circuit having a first state in which the first signal is passed to the first input, and having a second state in which the first signal is prevented from being passed to the first input;

a second pass circuit having a first state in which the second signal is prevented from being passed to the second input, and having a second state in which the second signal is passed to the second input.

4. The dual-mode circuit of claim 3 further comprising:

a first control input on the first pass circuit for controlling the first pass circuit to be in a selected one of the first state and the second state of the first pass circuit;

a second control input on the second pass circuit for controlling the second pass circuit to be in a selected one of the first state and the second state of the second pass circuit.

5. The dual-mode circuit of claim 4 further comprising:

a control circuit configured to generate a first control signal for the first control input so as to control the first pass circuit to be in the first state during the first mode of operation and to be in the second state during the second mode of operation;

the control circuit further configured to generate a second control signal for the second control input so as to control the second pass circuit to be in the first state during the first mode of operation and to be in the second state during the second mode of operation.

6. The dual-mode circuit of claim 5 further comprising:

a third pass circuit having a first state in which a signal at an output of the driving inverter is prevented from being passed on, and having a second state in which the signal at the output of the driving inverter is passed on;

a third control input on the third pass circuit for controlling the third pass circuit to be in a selected one of the first state and the second state of the first pass circuit.

7. The dual-mode circuit of claim 6 wherein:

the control circuit is further configured to generate a third control signal to the third control input so as to control the third pass circuit to be in the first state during the first mode of operation and to be in the second state during the second mode of operation.

8. The dual-mode circuit of claim 7 wherein the second input signal and the signal at the output of the driving inverter together constitute a double ended input signal during the second mode of operation.

9. The dual-mode circuit of claim 1 further comprising:

a non-volatile memory configured for multi-level cell programming;

wherein the first signal at the first input comprises a value read from a lower page of a memory location of the non-volatile memory for the purpose of setting a validation threshold for a multi-level cell program operation.

10. The dual-mode circuit of claim 9 wherein the second signal at the second input comprises an input signal containing a bit to be written to the non-volatile memory.

11. A method comprising:

in a first mode of operation, latching a first signal received at a first input of a latch circuit to the latch circuit;

in a second mode of operation, inverting a second signal received at a second input using a driving inverter that forms part of the latch circuit;

operating in the first mode of operation some of the time, and operating in the second mode of operation some of the time.

12. The method of claim 11 further comprising:

enabling the first input while in the first mode of operation;

disabling the second input while in the first mode of operation;

disabling the first input while in the second mode of operation;

enabling the second input while in the second mode of operation.

13. The method of claim 12 further comprising:

generating a first control signal to enable the first input while in the first mode of operation, and disable the first input while in the second mode of operation;

generating a second control signal to disable the second input while in the first mode of operation, and enable the second while in the second mode of operation;

generating a third control signal to disable the signal at the output of the driving inverter from being passed on in the mode of operation, and to enable the signal at the output of the driving inverter to be passed on during the second mode of operation.

14. The method of claim 11 further comprising:

reading a value from a lower page of a memory location of a non-volatile memory, and using the value as the first signal;

setting a validation threshold for a multi-level cell program operation based on the value read.

15. The method of claim 11 further comprising:

receiving an input signal containing a bit to be written to the non-volatile memory, the second signal at the second input comprising the input signal.

16. The method of claim 11 further comprising:

using the second input signal and the signal at the output of the driving inverter together as a double ended input signal during the second mode of operation.