Semiconductor device and information processing system
First Claim
1. A semiconductor device comprising:
- a plurality of circuit blocks; and
a control circuit controlling a start timing of a large-current operation performed by each of said plurality of circuit blocks within a predetermined period, said large-current operation involving a relatively large current flowing from a power supply system as compared with other operations,wherein said control circuit controls a start timing for the large-current operation of each circuit block such that the waveform of the current flowing from said power supply system is shaped into a waveform of a half cycle of a sinusoidal wave, when said plurality of circuit blocks execute the large-current operations within the predetermined period.
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Accused Products
Abstract
A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
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Citations
17 Claims
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1. A semiconductor device comprising:
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a plurality of circuit blocks; and a control circuit controlling a start timing of a large-current operation performed by each of said plurality of circuit blocks within a predetermined period, said large-current operation involving a relatively large current flowing from a power supply system as compared with other operations, wherein said control circuit controls a start timing for the large-current operation of each circuit block such that the waveform of the current flowing from said power supply system is shaped into a waveform of a half cycle of a sinusoidal wave, when said plurality of circuit blocks execute the large-current operations within the predetermined period. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An information processing system comprising:
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a plurality of semiconductor devices; and a control device controlling a start timing of a large-current operation performed by each of said plurality of semiconductor devices within a predetermined period, said large-current operation involving a relatively large current flowing from a power supply system as compared with other operations, wherein said control device controls a start timing for the large-current operation of each semiconductor device such that the waveform of the current flowing from said power supply system is shaped into a waveform of a half cycle of a sinusoidal wave, when said plurality of semiconductor devices execute the large-current operations within the predetermined period. - View Dependent Claims (9, 10, 11, 12)
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13. A semiconductor device comprising:
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a plurality of memory banks each comprising a plurality of word lines, a plurality of bit lines, and a plurality of DRAM memory cells disposed at intersections of said plurality of word lines with said plurality of bit lines; and a refresh control circuit controlling refresh operations of said plurality of memory banks, wherein said plurality of memory banks, responsive to a refresh signal input thereto, activate/deactivate predetermined word lines, and said refresh control circuit, responsive to a common refresh signal for causing said plurality of memory banks to execute refresh operations, generates the refresh signal to said plurality of memory banks at different timings, and outputs the generated refresh signal to said plurality of memory banks such that the waveform of a current flowing from a power supply system is shaped into a waveform of a half cycle of a sinusoidal wave. - View Dependent Claims (14, 15, 16, 17)
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Specification