Reconfigurable memory module and method

• US 7,966,444 B2
• Filed: 10/15/2010
• Issued: 06/21/2011
• Est. Priority Date: 06/19/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US12/905,741
• Publication Number:
  US 20110029746A1
• Time in Patent Office: 249 Days
• Field of Search: 711/5, 711/168, 711/170
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Claims

1. A processor-based electronic system, comprising:

a processor operable to execute a plurality of different application programs;

a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller;

an input device coupled to the processor;

an output device coupled to the processor; and

a plurality of memory modules each coupled to the controller through a high speed link, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of groups; and

a memory hub coupled to the memory devices in each of the groups and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of data formats depending upon the application program being executed by the processor, each of the data formats corresponding to a respective number of groups of memory devices that are simultaneously accessed wherein the memory hubs in at least two of the memory modules are programmed to configure their respective memory modules in different data formats for use at the same time.

2. A processor-based electronic system, comprising:

a processor operable to execute a plurality of different application programs;

a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller;

an input device coupled to the processor;

an output device coupled to the processor; and

a plurality of memory modules coupled to the controller, each of the memory modules coupled to the controller through a high speed link, comprising;

a plurality of memory devices arranged in a plurality of groups; and

a memory hub coupled to the memory devices in each of the groups and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of modes depending upon the application program being executed by the processor, each of the modes corresponding to a respective number of groups of memory devices that are simultaneously accessed wherein the memory hubs in at least two of the memory modules are programmed to configure their respective memory module in different data formats for use at the same time.

3. A processor-based electronic system, comprising:

a processor;

a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller;

an input device coupled to the processor;

an output device coupled to the processor;

a memory access device other than the processor; and

a plurality of memory modules coupled to the processor, each of the memory modules coupled to the at least one memory access device other than the processor through a high speed link, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of groups; and

a memory hub coupled to the memory devices in each of the groups and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of different data formats depending upon whether the memory module is being accessed by the processor or the memory access device other than the processor, each of the different data formats corresponding to a respective number of groups of memory devices that are simultaneously accessed wherein the memory hubs in at least two of the memory modules are programmed to configure their respective memory module in different data formats for use at the same time.

4. The electronic system of claim 3 wherein a first of the plurality of memory hubs is accessed by the processor and is configured in a first data format, and a second of the plurality of memory hubs is accessed by the device other than the processor and is configured in a second data format data is different from the first data format.

5. A processor-based electronic system, comprising:

a processor;

a controller coupled to the processor, the controller being operable to receive a memory request from the processor and to transmit a corresponding memory request from the controller;

an input device coupled to the processor;

an output device coupled to the processor;

a memory access device other than the processor; and

a plurality of memory modules coupled to the processor each of the memory modules coupled to the at least one memory access device other than the processor through a high speed link, each of the memory modules comprising;

a plurality of memory devices arranged in a plurality of groups; and

a memory hub coupled to the memory devices in each of the groups and being operable to receive memory requests, the memory hub being programmable to configure the memory module in a plurality of modes depending upon whether the memory module is being accessed by the processor or the memory access device other than the processor, each of the modes corresponding to a respective number of groups of memory devices that are simultaneously accessed wherein the memory hubs in at least two of the memory modules are programmed to configure their respective memory module in different data formats for use at the same time.

6. The electronic system of claim 5 wherein a first of the plurality of memory hubs is accessed by the processor and is configured in a first mode, and a second of the plurality of memory hubs is accessed by the device other than the processor and is configured in a second mode that is different from the first mode.