Method and apparatus for active software disown of cache line's exlusive rights

• US 7,966,453 B2
• Filed: 12/12/2007
• Issued: 06/21/2011
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Webb, Charles Franklin, Jackson, Kathryn Marie, Shum, Chung-Lung Kevin
• Primary Examiner(s): PATEL, HETUL B
• Application Number:
  US11/954,374
• Publication Number:
  US 20090157965A1
• Time in Patent Office: 1,287 Days
• Field of Search: None
• US Class Current: 711/121
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/6042 Allocation of cache space to multiple users or processors
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor'"'"'s explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.

Claims

1. A method for operating a computer system having a storage controller and a processing unit have a cache memory involving various ownership states as to a cache line, which states include a read-only or shared state and an exclusive state for holding the line exclusively, for software-initiated modification by hardware while the line is in said exclusive state, comprising the steps of:

activating interface controls for allowing software running on said computer system to indicate to the processing unit that its storage modification of a particular cache line in the exclusive state is done, and will not be doing any modification for the time being, for an active software indication to disown a cache line'"'"'s exclusive rights, and

communicating with said storage controller said software indication that its storage modification of said particular cache line is done and that any modification will not be done for the time being,

executing a demote request with regard to said particular cache line indicated by said software indication in said processing unit to cause the processing unit to actively relinquish control of its exclusive ownership of said particular cache line, and

preemptively updating the ownership status in the storage controller of said particular cache line to a read-only or shared state and with said preemptive updating removing delays due to cross interrogates (XIs) that would have otherwise been encountered by another processor should that another processor request an exclusive ownership to the actively relinquished particular cache line.

2. The computer system according to claim 1 wherein the software running on said computer system sends a indication that its storage modification of a particular cache line in the exclusive state is done, and will not be doing any modification for the time being when the software application knows that this is the last point of update until some period of time later.

3. A computer system, comprising:

a computer system having a storage controller and a processing unit coupled to cache memory involving various ownership states as to a cache line, which states include a read-only or shared state and an exclusive state for holding the line exclusive for software modification by hardware during the time that the line is in said exclusive state, and interface controls for allowing software running on said computer system to indicate to the hardware of the processing unit that its storage modification of a particular cache line in the exclusive state is done, and will not be doing any modification for the time being, for an active software indication to disown a cache line'"'"'s exclusive rights, and

said interface controls having an interface receiving mechanism for communicating with said storage controller said software indication that its storage modification of said particular cache line is done and that any modification will not be done for the time being, said interface controls preventing a premature launch of a demote request,

and executing said a demote request with regard to said particular cache line indicated by said software indication in said processing unit to cause the processing unit to actively relinquish control of its exclusive ownership of said particular cache line and preemptively updating the ownership status in the storage controller of said particular cache line to a read-only or shared state and with said preemptive updating removing delays due to cross interrogates (XIs) that would have otherwise been encountered by another processor should that another processor request an exclusive ownership to the actively relinquished particular cache line.

4. The computer system of claim 3 wherein said interface control ensures all prior committed storage updates are sent and received in the storage controller before a demote update is taken place for the requested cache line and said interface controls prevent a premature launch of said demote request.

5. The computer system according to claim 3 wherein a demote request causes a storage controller to update its directory to show that no processor is currently owning the line exclusive, and thus can return the line exclusively to a processor of the computing system when said processor requests in a timely manner without waiting on getting a confirmation on a cross interrogate from a prior owning processor.

6. The computer system according to claim 3 wherein when software running in a processor decides to demote a cache line the demoting processor sends a demote request to the storage controller, and once a demote request is received, the storage controller processes the request as if a non-existing processor is requesting a cache line exclusive and will start a directory search and send a cross interrogate to the processor owning exclusive rights to the requested cache line to request a release of exclusive rights, and when the storage controller receives acknowledgement of the request, it updates its directory to indicate that the requested line is now exclusive to no one processor to actively demote the particular requested cache line to a read-only or shared state.

7. The computer system according to claim 3 wherein when a processor requests the particular cache line exclusive after a demote request has been implemented, the storage controller can allow the particular cache line to be made exclusive to the requesting processor and reply to the requesting processor with an exclusive response without cross interrogation towards another processor.

8. The computer system according to claim 7 wherein the processing system has a first and a second storage controller and processors associated with each of said storage, and wherein said first storage controller is on one chip and said second storage controller is on the same or another chip and when a processor associated with the first storage controller requests a particular line exclusive associated with a processor of said second storage controller, the first storage controller requests the line exclusively from said second storage controller, and then replies to the requesting processor with an exclusive response without acquiring any delay for cross interrogation towards the processor associated with said processor of said second storage controller.

9. The computer system according to claim 3 wherein a processor of the computer system has a private level 1 cache and when said private level 2 cache'"'"'s processor sends a demote request to its private level 2 cache, that private level 2 cache will lookup its directory and then send a release exclusive cross interrogate back and the private level 2cache'"'"'s processor will process the interrogate request, ensure no pending store to the requested line, and remove its directory status of exclusive ownership and acknowledge to the private level 2 cache that it has so done whereupon the private level 2 cache will ensure no pending store to the requested line, and also update its own directory to indicate no exclusive ownership and send a demote request to the storage controller, which then will update its directory to indicate that the line is now exclusive to no one.

10. The computer system according to claim 3 wherein a processor is a microprocessor core having an instruction dispatch, a fixed point unit and a load store unit, and wherein a demote request is performed by the cache subsystem and the processor executes a demote as a one cycle superscalar instruction that performs no architectural updates.

11. A computer system comprising:

a storage controller, a plurality of processors forming a processing unit and a cache subsystem, and a cache interface establishing a direct connection between a processor and a storage controller upon receipt of a demote request issued by a processor of the processing units, said demote request being in response to an active software indication provided via software input to disown a cache line'"'"'s exclusive rights of a processor to a particular cache line, and

preemptively updating the ownership status in said storage controller of said computer system for said particular cache line upon receipt of said demote request to a read-only or shared state with said preemptive updating removing delays due to cross interrogates (XIs) that would have otherwise been encountered by another processor should that another processor request an exclusive ownership to the actively relinquished particular cache line.

12. The computer system according to claim 11 wherein said storage controller upon receipt of a demote request said interface control ensures all prior committed storage updates are sent and received in the storage controller before a demote update is taken place for the requested cache line and said interface controls prevent a premature launch of said demote request.

13. A method of managing storage updates in a computer system, comprising:

providing via software input an active software indication to disown a particular cache line'"'"'s exclusive rights when that a particular cache line is no longer required for any further storage update by a processor owning said particular cache line for store access, and

treating said software indication that said particular cache line is no longer required for any further storage update as an indication that the processor is at the end of its last storage updating and can be demoted from its storage access status to be next used by any of various processes that are running on said computer system , and

preemptively updating the ownership status in a storage controller of said computer system for said particular cache line to a read-only or shared state with said preemptive updating removing delays due to cross interrogates (XIs) that would have otherwise been encountered by another processor should that another processor request an exclusive ownership to the actively relinquished particular cache line.

14. The method according to claim 13 wherein the software indication includes an indication of the logical address.

15. The method according to claim 14 wherein said indication is a new opcode or instruction having code-points used for indicating that the indication is for a demote instruction.

16. A method according to claim 13 wherein said method is used in a computer system having a microprocessor having an instruction dispatch unit, a fixed point unit and a load store, and includes the steps of:

loading a cache subsystem with demote requests to be performed by the cache subsystem, and causing the processor to demote an exclusive particular cache line to a read-only or shared state preemptively updating the ownership status in the storage controller of said processor.

17. The method according to claim 16 wherein a processor core in response to a demote request executes a demote instruction as a one cycle superscalar instruction that performs no architectural updates.

18. The method according to claim 16 wherein the indication is provided by a connection between the processor and the storage controller.

19. The method according to claim 18 wherein the processor has a private level 2 cache and when said private level 2cache'"'"'s processor sends a demote request to its level 2 private cache, that private level 2cache will lookup its directory and then send a release exclusive cross interrogate back and the private level 2 cache'"'"'s processor will process the interrogate request, ensure no pending store to requested line, and remove its directory status of exclusive ownership and acknowledge to the private level 2 cache that it has so done whereupon the private level 2cache will ensure no pending store to requested line, and also update its own directory to indicate no exclusive ownership and send a demote request to the storage controller, which then will update its directory to indicate that the line is now exclusive to no one.