Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips
First Claim
1. A restorable plane-interleaved flash-memory system comprising:
- flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a physical block;
wherein the flash memory is further arranged into a plurality of planes that are plane-interleaved and accessible in parallel;
a volatile logical-physical mapping table storing mapping entries, wherein a mapping entry stores a logical address of data from a host and a physical block address (PBA) indicating a location of the data within the flash memory;
wherein the mapping entry further comprises a plane number and a page number;
a binary counter having a least-significant bit (LSB), a second LSB having a higher significance than the LSB, and middle bits having a higher significance than the second LSB;
a physical sequential address register, coupled to the binary counter, for storing a generated block number, wherein the middle bits have a higher significance than the second LSB in the generated block number, the second LSB being shifted to a higher bit position in the generated block number;
a page counter indicating the page number in the physical block in the flash memory;
an interleave incrementer for incrementing the LSB and the second LSB and not incrementing the middle bits when host data is to be written to a new page and all pages in a physical block of a fourth plane have not been yet filled;
a page incrementer for incrementing a page count when host data is to be written to a new page and when the LSB and the second LSB indicate the fourth plane and when empty pages are available in the physical block; and
a block incrementer for incrementing the middle bits when the LSB and the second LSB indicate the fourth plane and no empty pages are available in the physical block;
wherein the LSB and the second LSB are written to the mapping entry as the plane number, and the page count is written to the mapping entry as the page number when host data is written to the physical block corresponding to the mapping entry;
wherein the generated block number is written to the mapping entry as the physical block address, the generated block number having the second LSB shifted to a most-significant bit (MSB) of the physical block address;
a table restorer, coupled to the physical sequential address register, for restoring mapping entries in the volatile logical-physical mapping table by accessing blocks of the flash memory in a plane-interleaved order determined by the physical sequential address register,whereby the volatile logical-physical mapping table is restored from flash memory in the plane-interleaved order using the second LSB as a most-significant bit (MSB) of the physical block address.
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Accused Products
Abstract
A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
22 Citations
16 Claims
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1. A restorable plane-interleaved flash-memory system comprising:
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flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a physical block; wherein the flash memory is further arranged into a plurality of planes that are plane-interleaved and accessible in parallel; a volatile logical-physical mapping table storing mapping entries, wherein a mapping entry stores a logical address of data from a host and a physical block address (PBA) indicating a location of the data within the flash memory; wherein the mapping entry further comprises a plane number and a page number; a binary counter having a least-significant bit (LSB), a second LSB having a higher significance than the LSB, and middle bits having a higher significance than the second LSB; a physical sequential address register, coupled to the binary counter, for storing a generated block number, wherein the middle bits have a higher significance than the second LSB in the generated block number, the second LSB being shifted to a higher bit position in the generated block number; a page counter indicating the page number in the physical block in the flash memory; an interleave incrementer for incrementing the LSB and the second LSB and not incrementing the middle bits when host data is to be written to a new page and all pages in a physical block of a fourth plane have not been yet filled; a page incrementer for incrementing a page count when host data is to be written to a new page and when the LSB and the second LSB indicate the fourth plane and when empty pages are available in the physical block; and a block incrementer for incrementing the middle bits when the LSB and the second LSB indicate the fourth plane and no empty pages are available in the physical block; wherein the LSB and the second LSB are written to the mapping entry as the plane number, and the page count is written to the mapping entry as the page number when host data is written to the physical block corresponding to the mapping entry; wherein the generated block number is written to the mapping entry as the physical block address, the generated block number having the second LSB shifted to a most-significant bit (MSB) of the physical block address; a table restorer, coupled to the physical sequential address register, for restoring mapping entries in the volatile logical-physical mapping table by accessing blocks of the flash memory in a plane-interleaved order determined by the physical sequential address register, whereby the volatile logical-physical mapping table is restored from flash memory in the plane-interleaved order using the second LSB as a most-significant bit (MSB) of the physical block address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A flash-memory controller comprising:
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multi-level-cell (MLC) flash memory means for storing multiple bits of data per physical flash-memory cell, arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a block; volatile logical-physical mapping table means for storing mapping entries, wherein a mapping entry stores a logical address of data from a host and a physical block address (PBA) indicating a location of the data within the MLC flash memory means and a page number of a page within the physical block; volatile usage table means for storing valid bits for pages in the MLC flash memory means, wherein a valid bit for a page in the MLC flash memory means indicates a valid state when the page contains valid data, a stale state when the page contains data that has been replaced by newer data stored in a different page in the MLC flash memory means, and an erased state when the page has been erased and not yet written with data from the host; physical sequential address counter means for generating physical block addresses in a high-low plane-interleaved sequence wherein a low interleave bit is toggled twice as frequently as a high interleave bit, wherein the PBA is formed from the high interleave bit, middle bits, and the low interleave bit, wherein the high interleave bit has a higher significance than the middle bits, and the middle bits have higher significance than the low interleave bit in the PBA; middle increment means for incrementing the middle bits only when all pages in a block have been written; low plane increment means for incrementing the low interleave bit for each new page of data written to the MLC flash memory means; high plane increment means for incrementing the high interleave bit for every second new page of data written to the MLC flash memory means; and table restore means, coupled to the physical sequential address counter means, for restoring mapping entries in the volatile logical-physical mapping table means by accessing blocks of the MLC flash memory means in a plane-interleaved order determined by the physical sequential address counter means. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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Specification