Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips

• US 7,966,462 B2
• Filed: 10/12/2007
• Issued: 06/21/2011
• Est. Priority Date: 08/04/1999
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Ma, Abraham C., Lee, Charles C., Chow, David Q., Yu, Frank
• Primary Examiner(s): RUTZ, JARED IAN
• Application Number:
  US11/871,627
• Publication Number:
  US 20080034154A1
• Time in Patent Office: 1,348 Days
• Field of Search: 711/5, 711/103, 711/127, 711/157, 711/170, 711/200, 711/202, 711217-219
• US Class Current: 711/157
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2211/5649 Multilevel memory with plate line or layer, e.g. in order to lower programming voltages

Abstract

A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

Claims

1. A restorable plane-interleaved flash-memory system comprising:

flash memory arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a physical block;

wherein the flash memory is further arranged into a plurality of planes that are plane-interleaved and accessible in parallel;

a volatile logical-physical mapping table storing mapping entries, wherein a mapping entry stores a logical address of data from a host and a physical block address (PBA) indicating a location of the data within the flash memory;

wherein the mapping entry further comprises a plane number and a page number;

a binary counter having a least-significant bit (LSB), a second LSB having a higher significance than the LSB, and middle bits having a higher significance than the second LSB;

a physical sequential address register, coupled to the binary counter, for storing a generated block number, wherein the middle bits have a higher significance than the second LSB in the generated block number, the second LSB being shifted to a higher bit position in the generated block number;

a page counter indicating the page number in the physical block in the flash memory;

an interleave incrementer for incrementing the LSB and the second LSB and not incrementing the middle bits when host data is to be written to a new page and all pages in a physical block of a fourth plane have not been yet filled;

a page incrementer for incrementing a page count when host data is to be written to a new page and when the LSB and the second LSB indicate the fourth plane and when empty pages are available in the physical block; and

a block incrementer for incrementing the middle bits when the LSB and the second LSB indicate the fourth plane and no empty pages are available in the physical block;

wherein the LSB and the second LSB are written to the mapping entry as the plane number, and the page count is written to the mapping entry as the page number when host data is written to the physical block corresponding to the mapping entry;

wherein the generated block number is written to the mapping entry as the physical block address, the generated block number having the second LSB shifted to a most-significant bit (MSB) of the physical block address;

a table restorer, coupled to the physical sequential address register, for restoring mapping entries in the volatile logical-physical mapping table by accessing blocks of the flash memory in a plane-interleaved order determined by the physical sequential address register,

whereby the volatile logical-physical mapping table is restored from flash memory in the plane-interleaved order using the second LSB as a most-significant bit (MSB) of the physical block address.

2. The restorable plane-interleaved flash-memory system of claim 1 further comprising:

a stale threshold comparator for comparing a number of stale pages in a stale block in the flash memory to a stale threshold;

a background recycler activated for the stale block in the flash memory having the number of stale pages exceeding the stale threshold;

a recycle buffer receiving valid pages from the stale block;

a page packer, receiving additional pages from a host or from another stale block, for merging additional data with the valid pages in the recycle buffer to generate a merged block;

a merged block writer that writes the merged block from the recycle buffer into the flash memory; and

a block eraser that erased the stale block for reuse.

3. The restorable plane-interleaved flash-memory system of claim 2 further comprising:

a mapping entry updater for updating mapping entries in the volatile logical-physical mapping table storing mapping entries in response to the background recycler.

4. The restorable plane-interleaved flash-memory system of claim 1 wherein pages for the plurality of planes are written in parallel at a same time;

wherein a first page is written to a first physical block in a first plane having a first generated block number;

wherein a second page is written to a second physical block in a second plane having a second generated block number that is one greater than the first generated block number;

wherein a third page is written to a third physical block in a third plane having a third generated block number that is 2^x greater than the first generated block number, wherein X is a number of bits for the middle bits;

wherein a fourth page is written to a fourth physical block in the fourth plane having a fourth generated block number that is one greater than the third generated block number;

wherein the first plane, the second plane, the third plane, and the fourth plane are in the plurality of planes,

whereby generated block numbers for the third and fourth planes are 2^x greater than the generated block numbers for the first and second planes.

5. The restorable plane-interleaved flash-memory system of claim 4 wherein X is 12 and the generated block numbers for the third and fourth planes are 4096 greater than the generated block numbers for the first and second planes.

6. The restorable plane-interleaved flash-memory system of claim 1 further comprising:

a page buffer for storing data to be written to the flash memory;

an error-correction-code (ECC) generator, coupled to the page buffer, for generating ECC bytes for a page of sectors being written to the flash memory.

7. The restorable plane-interleaved flash-memory system of claim 6 further comprising:

a zero-writer, coupled to a page register, for writing zeros to sectors that are not being written with data in a page ready to be written from the page register to the flash memory,

whereby empty sectors are zeroed before writing to the flash memory.

8. The restorable plane-interleaved flash-memory system of claim 7 wherein the flash memory comprises multi-level-cell (MLC) flash memory that comprises physical memory cells that each store more than one bit of data;

wherein each page in the flash memory is writeable only once between erases and wherein the flash memory writes host data to pages in a sequential order of pages within a physical block;

wherein out-of-sequence page writing is prohibited by the flash memory.

9. The restorable plane-interleaved flash-memory system of claim 8 further comprising:

an interface circuit which comprises a Compact Flash (CF) interface circuit, a Universal-Serial-Bus (USB) interface circuit, a PCI-Express interface circuit, an Integrated Drive Electronics (IDE) interface circuit, a Serial Advanced Technology Attachment (SATA) interface circuit, or an external SATA Interface Circuit.

10. A flash-memory controller comprising:

multi-level-cell (MLC) flash memory means for storing multiple bits of data per physical flash-memory cell, arranged as blocks of multiple pages, wherein pages are written and blocks are erased, wherein individual pages are not individually erasable except by erasing all pages in a block;

volatile logical-physical mapping table means for storing mapping entries, wherein a mapping entry stores a logical address of data from a host and a physical block address (PBA) indicating a location of the data within the MLC flash memory means and a page number of a page within the physical block;

volatile usage table means for storing valid bits for pages in the MLC flash memory means, wherein a valid bit for a page in the MLC flash memory means indicates a valid state when the page contains valid data, a stale state when the page contains data that has been replaced by newer data stored in a different page in the MLC flash memory means, and an erased state when the page has been erased and not yet written with data from the host;

physical sequential address counter means for generating physical block addresses in a high-low plane-interleaved sequence wherein a low interleave bit is toggled twice as frequently as a high interleave bit, wherein the PBA is formed from the high interleave bit, middle bits, and the low interleave bit, wherein the high interleave bit has a higher significance than the middle bits, and the middle bits have higher significance than the low interleave bit in the PBA;

middle increment means for incrementing the middle bits only when all pages in a block have been written;

low plane increment means for incrementing the low interleave bit for each new page of data written to the MLC flash memory means;

high plane increment means for incrementing the high interleave bit for every second new page of data written to the MLC flash memory means; and

table restore means, coupled to the physical sequential address counter means, for restoring mapping entries in the volatile logical-physical mapping table means by accessing blocks of the MLC flash memory means in a plane-interleaved order determined by the physical sequential address counter means.

11. The flash-memory controller of claim 10 further comprising:

plane-interleaved access means for accessing the MLC flash memory means arranged as a first plane, a second plane, a third plane, and a fourth plane in the plane-interleaved order, using the high interleave bit and the low interleave bit to select from among the first, second, third, and fourth planes,

whereby flash memory is accessed in a high-low plane-interleaved order of physical blocks.

12. The flash-memory controller of claim 11 further comprising:

stale threshold compare means for comparing a number of stale pages in a stale block in the MLC flash memory means to a stale threshold;

background recycle means for recycling stale blocks, activated for the stale block in the MLC flash memory means, wherein the stale block has the number of stale pages exceeding the stale threshold;

recycle buffer means for receiving valid pages from the stale block;

page packing means, receiving additional pages from a host or from another stale block, for merging additional data with the valid pages in the recycle buffer means to generate a merged block;

merged block write means for writing the merged block from the recycle buffer into the MLC flash memory means; and

block erase means for erasing the stale block for reuse.

13. The flash-memory controller of claim 12 further comprising:

page buffer means for storing data to be written to the MLC flash memory means;

error-correction-code (ECC) generate means, coupled to the page buffer means, for generating ECC bytes for a page of sectors being written to the MLC flash memory means.

14. The flash-memory controller of claim 13 further comprising:

zero-writer means, coupled to a page register, for writing zeros to sectors that are not being written with data in a page ready to be written from the page register to the MLC flash memory means,

whereby empty sectors are zeroed before writing to the MLC flash memory means.

15. The flash-memory controller of claim 12 wherein the volatile logical-physical mapping table means further comprises:

a plurality of sector table means, each for storing mapping entries having a same logical sector offset within logical blocks identified by the logical address; and

logical table means for storing logical valid bits that indicate valid logical sectors for each logical block having data stored in the MLC flash memory means;

wherein a sector table means in the plurality of sector table means is for storing a valid mapping entry when the logical valid bit corresponding to the same logical sector offset for the sector table means indicates that the data is stored in the MLC flash memory means.

16. The flash-memory controller of claim 11 further comprising:

page counter means for incrementing the page number when all four planes have been accessed and all pages in the block have not been written.