Method for selectively retrieving column redundancy data in memory device

• US 7,966,532 B2
• Filed: 03/31/2009
• Issued: 06/21/2011
• Est. Priority Date: 10/26/2008
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Sojourner, Doug, Fasoli, Luca, Bottelli, Aldo
• Primary Examiner(s): Gaffin; Jeffrey A
• Assistant Examiner(s): NGUYEN, STEVE N
• Application Number:
  US12/414,935
• Publication Number:
  US 20100107004A1
• Time in Patent Office: 812 Days
• Field of Search: 714710-711, 714718-723, 365200-201
• US Class Current: 714/723
• CPC Class Codes: G11C 29/802 by encoding redundancy signals
• CPC Class Codes: G11C 29/812 using a reduced amount of fuses
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.

Claims

1. A method for operating a memory device, comprising:

in response to a request to access storage elements in a particular set of storage elements of the memory device, loading byte redundancy data for the particular set from at least one non-volatile storage location of the memory device to a volatile storage location of the memory device, without loading byte redundancy data for other sets, the at least one non-volatile storage location stores byte redundancy data for the particular set and for other sets of storage elements of the memory device, the byte redundancy data for the particular set and for the other sets provides redundancy for N defects, the volatile storage location is sized to store M<

N entries to accommodate M defects, and M and N are integers greater than one; and

accessing the storage elements in the particular set using the byte redundancy data for the particular set.

2. The method of claim 1, further comprising:

in response to a request to access storage elements in an additional set of storage elements which is part of the other sets of storage elements, loading byte redundancy data for the additional set to the volatile storage location, the byte redundancy data for the additional set replaces the byte redundancy data for the particular set; and

accessing the storage elements in the additional set using the byte redundancy data for the additional set.

3. The method of claim 1, wherein the at least one non-volatile storage location comprises multiple non-volatile storage locations of the memory device, and the byte redundancy data for the particular set comprises redundant bytes which are loaded from the multiple non-volatile storage locations of the memory device, the method further comprising:

performing a majority voting process to ascertain bit values of the redundant bytes.

4. The method of claim 1, wherein:

the byte redundancy data for the particular set provides an address of at least one defective byte of storage elements of the particular set, and an address of at least one associated replacement byte of storage elements.

5. The method of claim 4, wherein:

the address includes a byte address.

6. The method of claim 1, wherein:

M is an expected maximum number of defects per set for all sets of storage elements in the memory device.

7. The method of claim 1, wherein:

a definition of which storage elements are included in the particular set of storage elements and the other sets of storage elements is configurable in the memory device.

8. The method of claim 1, further comprising:

reloading the volatile storage location with new byte redundancy data each time a different set of storage elements is accessed.

9. The method of claim 1, wherein:

each set comprises one or more logical blocks of storage elements on a common die.

10. The method of claim 1, wherein:

the accessing of the storage elements in the particular set comprises at least one of reading and writing.

11. The method of claim 1, wherein:

the storage elements are non-volatile storage elements.

12. A memory device, comprising:

a plurality of sets of storage elements, including a particular set of storage elements and other sets of storage elements;

at least one non-volatile storage location which stores byte redundancy data for the particular set and for the other sets, the byte redundancy data for the particular set and for the other sets provides redundancy for N defects;

a volatile storage location which is sized to store M<

N entries to accommodate M defects, where M and N are integers greater than one; and

at least one control circuit, the at least one control circuit;

(a) receives a request to access storage elements in the particular set, and (b) in response to the request, (i) loads byte redundancy data for the particular set from the at least one non-volatile storage location to the volatile storage location, without loading byte redundancy data for the other sets of storage elements, and (ii) accesses the storage elements in the particular set using the byte redundancy data for the particular set.

13. The memory device of claim 12, wherein:

the plurality of sets of storage elements and the at least one non-volatile storage location are on a chip; and

the volatile storage location is off the chip.

14. The memory device of claim 13, wherein:

the at least one control circuit comprises a controller which is off the chip.

15. The memory device of claim 12, wherein:

the plurality of sets of storage elements and the at least one non-volatile storage location are on a chip in a memory array.

16. The memory device of claim 15, wherein:

the plurality of sets of storage elements are in non-redundant columns of the memory array, and the at least one non-volatile storage location is in redundant columns of the memory array.

17. The memory device of claim 12, wherein:

the request to access storage elements in the particular set of storage elements is a read or write request which is received from a host.

18. The memory device of claim 12, wherein:

M is an expected maximum number of defects per set for all sets of storage elements in the memory device.

19. The memory device of claim 12, wherein:

the at least one control circuit reloads the volatile storage location with new byte redundancy data each time a different set of storage elements is accessed.

20. The memory device of claim 12, wherein:

the storage elements are non-volatile storage elements.