Generic non-volatile service layer

• US 7,966,581 B2
• Filed: 10/16/2008
• Issued: 06/21/2011
• Est. Priority Date: 10/16/2008
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Li, Hai, Liu, Hongyue, Xi, Haiwen, Chen, Yiran, Setiadi, Dadi
• Primary Examiner(s): Levin; Naum
• Application Number:
  US12/252,564
• Publication Number:
  US 20100100857A1
• Time in Patent Office: 978 Days
• Field of Search: 716/51, 716/106, 716/111, 714/25, 714/30, 713/151
• US Class Current: 716/51
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]

Abstract

Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.

Claims

1. An apparatus comprising a three dimensional integrated circuit comprising a generic non-volatile service layer affixed to a host layer in a multi-layer integrated circuit chip package, wherein the generic non-volatile service layer is configured in a first configuration to test the host layer using a test pattern stored in a non-volatile memory, and then to be reconfigured in a security protocol where the host layer uses at least one security component on the service layer to restrict access to the integrated circuit as a permanent non-testing functional component of the integrated circuit.

2. The apparatus of claim 1, wherein the non-volatile memory is a spin torque random access memory (STRAM) of said generic service layer.

3. The apparatus of claim 1, wherein the non-volatile memory is a resistive random access memory (RRAM) of said generic service layer.

4. The apparatus of claim 1, further comprising a control circuit which initially configures the service layer in the first configuration, executes said testing of the host layer, and then places the service layer in the second configuration.

5. The apparatus of claim 1, wherein the non-testing functional component comprises a field programmable gate array (FPGA).

6. The apparatus of claim 5, wherein an array of look-up tables are each connected to a delay flip flop in the generic service layer.

7. The apparatus of claim 1, wherein the non-testing functional component is a redundancy correction for the host layer.

8. The apparatus of claim 1, wherein the generic non-volatile service layer comprises an array of unit test structures when configured in the first configuration to test the host layer.

9. The apparatus of claim 1, wherein the at least one security component is a key, identification, handler, or configuration file that communicates with the integrated circuit.

10. The apparatus of claim 1, wherein the security protocol restricts access to the integrated circuit by matching an input key to a device specific key.

11. An apparatus comprising a printed circuit board which operationally supports a multi-layer integrated circuit chip package arranged as a three dimensional integrated circuit and comprising a host layer and a generic non-volatile service layer, the service layer comprising a non-volatile memory which stores a test pattern adapted to test the host layer during a testing mode of operation and which stores security component data adapted to prevent access to the host layer by an unauthorized user using a selected security protocol during a performance mode of operation.

12. The apparatus of claim 11, in which the security component data is further adapted to facilitate access to the host layer by an authorized user during said performance mode of operation.

13. The apparatus of claim 11, in which the non-volatile memory is characterized as an array of spin torque random access memory (STRAM) memory cells.

14. The apparatus of claim 11, in which the service layer is adapted to be permanently placed into said performance mode of operation after execution of said testing mode of operation.

15. The apparatus of claim 11, in which the service layer further comprises a control circuit which respectively selects the testing and performance modes of operation.

16. The apparatus of claim 11, in which the security component data comprises a key, identification value, handler, or a configuration file.