Fabricating method of thin film transistor array substrate
First Claim
1. A fabricating method of a thin film transistor array substrate, comprising:
- providing a substrate, wherein the substrate has a pixel region and a bonding pad region located surrounding the pixel region;
forming a patterned polysilicon layer within the pixel region on the substrate, wherein the patterned polysilicon layer comprises a source and a drain;
forming a first patterned insulating layer to cover the patterned polysilicon layer;
forming a first patterned transparent conductive layer on the first patterned insulating layer;
forming a first metal layer on the first patterned transparent conductive layer, wherein the first metal layer is partially disposed on the first patterned transparent conductive layer and comprises a gate, a scan line electrically connected to the gate and a common line disposed within the pixel region, and a part of the first patterned transparent conductive layer is disposed under the common line;
forming a second patterned insulating layer to cover the first metal layer, wherein the first patterned insulating layer and the second patterned insulating layer have a first contact hole to expose the drain;
forming a second patterned transparent conductive layer on the second patterned insulating layer, wherein a part of the second patterned transparent conductive layer is electrically connected to the drain via the first contact hole;
forming a second metal layer on the second patterned transparent conductive layer, wherein the second metal layer is partially disposed on the second patterned transparent conductive layer and the second metal layer comprises a data line electrically connected to the source, and a part of the second patterned transparent conductive layer is disposed under the data line;
forming a third patterned insulating layer to cover the second metal layer, wherein the third patterned insulating layer has a second contact hole to expose the second patterned transparent conductive layer electrically connected to the drain; and
forming a third patterned transparent conductive layer on the third patterned insulating layer, wherein the third patterned transparent conductive layer comprises a pixel electrode located within the pixel region, and the pixel electrode is electrically connected to the second patterned transparent conductive layer via the second contact hole.
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Abstract
A fabricating method of a TFT array substrate includes following steps: providing a substrate having a pixel region and a bonding pad region surrounding the pixel region; forming a patterned polysilicon layer within the pixel region on the substrate; forming a first patterned insulating layer to cover the patterned polysilicon layer; forming a first patterned transparent conductive layer on the first patterned insulating layer; forming a first metal layer on the first patterned transparent conductive layer; forming a second patterned insulating layer to cover the first metal layer; forming a second patterned transparent conductive layer on the second patterned insulating layer; forming a second metal layer on the second patterned transparent conductive layer; forming a third patterned insulating layer to cover the second metal layer; and forming a third patterned transparent conductive layer on the third patterned insulating layer.
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Citations
9 Claims
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1. A fabricating method of a thin film transistor array substrate, comprising:
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providing a substrate, wherein the substrate has a pixel region and a bonding pad region located surrounding the pixel region; forming a patterned polysilicon layer within the pixel region on the substrate, wherein the patterned polysilicon layer comprises a source and a drain; forming a first patterned insulating layer to cover the patterned polysilicon layer; forming a first patterned transparent conductive layer on the first patterned insulating layer; forming a first metal layer on the first patterned transparent conductive layer, wherein the first metal layer is partially disposed on the first patterned transparent conductive layer and comprises a gate, a scan line electrically connected to the gate and a common line disposed within the pixel region, and a part of the first patterned transparent conductive layer is disposed under the common line; forming a second patterned insulating layer to cover the first metal layer, wherein the first patterned insulating layer and the second patterned insulating layer have a first contact hole to expose the drain; forming a second patterned transparent conductive layer on the second patterned insulating layer, wherein a part of the second patterned transparent conductive layer is electrically connected to the drain via the first contact hole; forming a second metal layer on the second patterned transparent conductive layer, wherein the second metal layer is partially disposed on the second patterned transparent conductive layer and the second metal layer comprises a data line electrically connected to the source, and a part of the second patterned transparent conductive layer is disposed under the data line; forming a third patterned insulating layer to cover the second metal layer, wherein the third patterned insulating layer has a second contact hole to expose the second patterned transparent conductive layer electrically connected to the drain; and forming a third patterned transparent conductive layer on the third patterned insulating layer, wherein the third patterned transparent conductive layer comprises a pixel electrode located within the pixel region, and the pixel electrode is electrically connected to the second patterned transparent conductive layer via the second contact hole. - View Dependent Claims (2, 3, 4, 5)
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6. A fabricating method of a thin film transistor array substrate, comprising:
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providing a substrate, wherein the substrate has a pixel region and a bonding pad region located surrounding the pixel region; forming a first patterned transparent conductive layer on the substrate; forming a first metal layer on a part of the first patterned transparent conductive layer, wherein the first metal layer comprises a gate, a scan line electrically connected to the gate and a common line within the pixel region, and a part of the first patterned transparent conductive layer is disposed under the common line; forming a first insulating layer to cover the first metal layer; forming a channel layer on the first insulating layer over the gate; forming a second patterned transparent conductive layer on the substrate; forming a second metal layer on a part of the second patterned transparent conductive layer, wherein the second metal layer comprises a source and a drain respectively disposed at two sides of the channel layer and a data line electrically connected to the source, wherein a part of the second patterned transparent conductive layer is disposed under the drain; forming a second insulating layer to cover the second metal layer and expose the second patterned transparent conductive layer under the drain; and forming a third patterned transparent conductive layer on the substrate, wherein the third patterned transparent conductive layer comprises a pixel electrode electrically connected to the second patterned transparent conductive layer under the drain. - View Dependent Claims (7, 8, 9)
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Specification