Semiconductor device and manufacturing method thereof

• US 7,968,890 B2
• Filed: 01/22/2008
• Issued: 06/28/2011
• Est. Priority Date: 07/22/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Arai, Yasuyuki, Suzawa, Hideomi, Ono, Koji, Yamazaki, Shunpei
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US12/009,754
• Publication Number:
  US 20090101901A1
• Time in Patent Office: 1,253 Days
• Field of Search: 257/59, 257/72, 257/83, 257/257, 257/290
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1237 with a different composition, shape, layout or thickness of the gate insulator in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1277 using a crystallisation promoting species, e.g. local introduction of Ni catalyst
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

Claims

1. A semiconductor device comprising:

a pixel section comprising a pixel TFT over a substrate;

a driver circuit comprising an n-channel TFT and a p-channel TFT over the substrate;

wherein each of the pixel TFT and the n-channel TFT comprises;

a semiconductor layer comprising a channel forming region, a pair of LDD regions in contact with the channel forming region, and source and drain regions disposed on the outside of the pair of LDD regions;

a gate insulating film provided over the semiconductor layer, wherein a thickness of the gate insulating film over the channel region is thicker than a thickness of the gate insulating film over each of the source and drain regions; and

a gate electrode provided over the gate insulating film, and overlapping a portion of the pair of LDD regions, and

wherein the p-channel TFT comprises;

a semiconductor layer comprising a channel forming region, a pair of LDD regions in contact with the channel forming region, and source and drain regions disposed on the outside of the pair of LDD regions;

a gate insulating film provided over the semiconductor layer, wherein a thickness of the gate insulating film over the channel region is thicker than a thickness of the gate insulating film over each of the source and drain regions;

a gate electrode provided over the gate insulating film, and overlapping the pair of LDD regions, entirely.

2. A semiconductor device according to claim 1, wherein the gate electrodes of the pixel TFT, the p-channel TFT and the n-channel TFT comprise a heat resistant conductive material and a gate wiring that is connected to the gate electrode is extended from the driver circuit comprises a low resistivity conductive material.

3. A semiconductor device according to claim 2, wherein the heat resistant conductive material is selected from a group consisting of an element selected from tantalum (Ta), titanium (Ti) or tungsten (W);

a compound which comprises the element;

a compound which comprises a combination of the element;

a nitride which comprises the element; and

a silicide which comprises the element.

4. A semiconductor device according to claim 1, wherein each of the gate electrodes of the p-channel TFT and the n-channel TFT has a tapered portion.

5. A semiconductor device according to claim 4, wherein an angle of the tapered portion is between 5 and 45°

.

6. A semiconductor device according to claim 1, wherein the semiconductor device is applied to an electronic appliance selected from a group consisting of a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, an electronic game machine, and a projector.

7. A semiconductor device according to claim 1, wherein a concentration of an impurity element in the LDD region are set to become higher as the distance from channel forming regions that are in contact increase.

8. A semiconductor device according to claim 1, wherein the gate insulating film comprises in insulating film containing silicon.