Logic non-volatile memory cell with improved data retention ability
First Claim
1. A non-volatile memory cell comprising:
- a semiconductor substrate;
a first transistor comprising;
a first dielectric over the semiconductor substrate; and
a first floating gate over the first dielectric;
a second transistor electrically coupled to the first transistor, the second transistor comprising;
a second dielectric over the semiconductor substrate; and
a second floating gate over the second dielectric, wherein the first and the second floating gates are electrically disconnected;
a first capacitor;
a second capacitor electrically coupled to the first capacitor;
a third capacitor;
a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third, and the fourth capacitors comprises the semiconductor substrate as one of capacitor plates;
a third transistor as a selector of the non-volatile memory cell, wherein the third transistor is electrically coupled to the first and the second transistors, and wherein sources of the first and the second transistors are connected to each other when the selector is turned on and when the selector is turned off, and drains of the first and the second transistors are connected to each other when the selector is turned on and when the selector is turned off; and
a bit line electrically connected to a first source/drain region of the third transistor, wherein a second source/drain region of the third transistor is electrically connected to a second source/drain region of each of the first and the second transistors.
1 Assignment
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Accused Products
Abstract
A memory cell includes a semiconductor substrate; and a first, a second, and a third transistor. The first transistor includes a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric. The second transistor is electrically coupled to the first transistor and includes a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric. The first and the second floating gates are electrically disconnected. The memory cell further includes a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third and the fourth capacitors includes the semiconductor substrate as one of the capacitor plates. The third transistor is a selector of the memory cell and is electrically coupled to the first and the second transistors.
36 Citations
19 Claims
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1. A non-volatile memory cell comprising:
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a semiconductor substrate; a first transistor comprising; a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric; a second transistor electrically coupled to the first transistor, the second transistor comprising; a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric, wherein the first and the second floating gates are electrically disconnected; a first capacitor; a second capacitor electrically coupled to the first capacitor; a third capacitor; a fourth capacitor electrically coupled to the third capacitor, wherein each of the first, the second, the third, and the fourth capacitors comprises the semiconductor substrate as one of capacitor plates; a third transistor as a selector of the non-volatile memory cell, wherein the third transistor is electrically coupled to the first and the second transistors, and wherein sources of the first and the second transistors are connected to each other when the selector is turned on and when the selector is turned off, and drains of the first and the second transistors are connected to each other when the selector is turned on and when the selector is turned off; and a bit line electrically connected to a first source/drain region of the third transistor, wherein a second source/drain region of the third transistor is electrically connected to a second source/drain region of each of the first and the second transistors. - View Dependent Claims (2, 3, 4, 5, 6, 17)
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7. A non-volatile memory cell comprising:
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a semiconductor substrate; a first transistor comprising; a first dielectric over the semiconductor substrate; and a first floating gate over the first dielectric; a second transistor electrically coupled to the first transistor, the second transistor comprising; a second dielectric over the semiconductor substrate; and a second floating gate over the second dielectric, wherein the first and the second floating gates are electrically disconnected, and wherein source regions of the first and the second transistors are interconnected, and drain regions of the first and the second transistors are interconnected; a first capacitor comprising the first floating gate as one of capacitor plates; a second capacitor comprising the first floating gate as one of capacitor plates; a third capacitor comprising the second floating gate as one of capacitor plates; a fourth capacitor comprising the second floating gate as one of capacitor plates; a third transistor comprising a first source/drain region connected to one of the interconnected source regions and the interconnected drain regions of the first and the second transistors; a third floating gate over and electrically disconnected from the first and the second floating gates; a fifth capacitor comprising the third floating gate as one of capacitor plates; and a sixth capacitor comprising the third floating gate as one of capacitor plates. - View Dependent Claims (8, 9, 10, 11, 18, 19)
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12. A non-volatile memory cell comprising:
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a semiconductor substrate; a first dielectric over the semiconductor substrate; a first floating gate over the first dielectric; a second dielectric over the semiconductor substrate; a second floating gate over the second dielectric and electrically disconnected from the first floating gate; a first, a second, and a third implanted region in the semiconductor substrate and adjacent the first floating gate, wherein the first, the second, and the third implanted regions are isolated by insulation regions in the semiconductor substrate; a fourth, a fifth, and a sixth implanted region in the semiconductor substrate and adjacent the first and the second floating gates, wherein the fourth, the fifth, and the sixth implanted regions are isolated by the insulation regions; a seventh, a eighth, and a ninth implanted region in the semiconductor substrate and adjacent the second floating gate, wherein the seventh, the eighth, and the ninth implanted regions are isolated by the insulation regions; a third gate dielectric over the semiconductor substrate; a word line over the third gate dielectric; a tenth implanted region in the semiconductor substrate and adjacent the word line; and an eleventh implanted region in the semiconductor substrate and adjacent the word line, wherein the eleventh implanted region is electrically connected to the fifth implanted region. - View Dependent Claims (13, 14, 15, 16)
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Specification