High-voltage device structure

• US 7,968,938 B2
• Filed: 06/10/2005
• Issued: 06/28/2011
• Est. Priority Date: 06/14/2004
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Letavic, Theodore, Petruzzello, John
• Primary Examiner(s): Gebremariam; Samuel A
• Application Number:
  US11/629,766
• Publication Number:
  US 20080128743A1
• Time in Patent Office: 2,209 Days
• Field of Search: 257/328, 257/330, 257/329, 257/E29.118, 257/262, 257/E29.256
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates

Abstract

The present invention provides a vertical tapered dielectric high-voltage device (10) in which the device drift region is depicted by action of MOS field plates (30) formed in vertical trenches. The high-voltage device comprises: a substrate (32); a silicon mesa (20) formed on the substrate and having a stripe geometry, wherein the silicon mesa provides a drift region having a constant doping profile; a recessed gate (22) and source (SN) formed on the silicon mesa; a trench (26) adjacent each side of the silicon mesa; and a metal-dielectric field plate structure (12) formed in each trench; wherein each metal-dielectric field plate structure comprises a dielectric (28) and a metal field plate (30) formed over the dielectric, and wherein a thickness of the dielectric increases linearly through a depth of the trench to provide a constant longitudinal electric field.

Claims

1. A high-voltage device, comprising:

a substrate;

a silicon mesa formed on the substrate, wherein the silicon mesa provides a drift region having a constant doping profile;

a recessed gate and source formed on the silicon mesa;

a trench adjacent each side of the silicon mesa; and

a metal-dielectric field plate structure formed in each trench;

wherein each metal-dielectric field plate structure comprises a dielectric and a metal field plate formed over the dielectric, and wherein a thickness of the dielectric uniformly increases linearly through a portion of a depth of the trench, wherein the dielectric is configured to produce a constant longitudinal electric field through the portion of the depth of the trench.

2. The device of claim 1, wherein the silicon mesa comprises a stripe geometry.

3. The device of claim 1, wherein the thickness of the dielectric varies according to:

t_ox(x)=(E_x∈

₀∈

_ox)/(qN_dt_soi))x+c,

where E_x is longitudinal electric field, ∈

₀ is permittivity of free space, ∈

_ox is permittivity of the dielectric, q is magnitude of electronic charge, N_d is doping concentration in the drift region, t_soi is thickness of the silicon mesa, and c is a constant related to gate oxide-field plate transition.

4. The device of claim 1, wherein the device comprises an re-channel double-diffused metal oxide semiconductor transistor.

5. The device of claim 1, wherein the device comprises an insulated gate bipolar transistor.

6. The device of claim 1, wherein the substrate and the silicon mesa are of the same doping type.

7. The device of claim 1, wherein the substrate and the silicon mesa are of different doping types.

8. The device of claim 1, wherein a dielectric layer is provided over the metal field plate in the trench, and wherein the thickness of the dielectric layer decreases through the depth of the trench.

9. The device of claim 1, wherein a metal/conductor layer is provided over the metal field plate in the trench, and wherein a thickness of the metal/conductor layer decreases through the depth of the trench.

10. The device of claim 1, wherein the silicon mesa has a width of 3-5 pm, wherein the dielectric of the metal-dielectric field plate structure has a maximum thickness of 5.5-6.5 pm, and wherein the constant doping in the silicon mesa is 1.0-3.5×

10¹⁶ cm<sup>−

3</sup>.

11. The device of claim 1, wherein a 750 V device has a specific on-resistance in the range of 0.4-10.0 ohm mm².

12. A high-voltage device comprising:

a substrate;

a silicon stripe formed on the substrate;

a silicon mesa formed in the silicon stripe, wherein the silicon mesa provides a drift region having a constant doping profile;

a recessed gate and source formed on the silicon mesa;

a trench adjacent each side of the silicon stripe; and

a metal-dielectric field plate structure formed in each trench along the silicon stripe;

wherein each metal-dielectric field plate structure comprises a dielectric and a metal, field plate formed over the dielectric, and wherein a thickness of the dielectric uniformly increases linearly through a portion of a depth of the trench, wherein the dielectric is configured to produce a constant longitudinal electric field through the portion of the depth of the trench.

13. The device of claim 12, wherein the thickness of the dielectric varies according to:

t_ox(x)=(E_x∈

₀∈

_ox)/(qN_dt_soi))x+c,

where E_x is longitudinal electric field, ∈

₀ is permittivity of free space, ∈

_ox is permittivity of the dielectric, q is magnitude of electronic charge, N_d is doping concentration in the drift region, t_soi is thickness of the silicon stripe, and c is a constant related to gate oxide-field plate transition.

14. The device of claim 12, wherein the device comprises an n-channel double diffused metal oxide semiconductor transistor.

15. The device of claim 12, wherein the device comprises an insulated gate bipolar transistor.

16. The device of claim 12, wherein the silicon stripe has a width of 3-5 pm, wherein the dielectric of metal-dielectric field plate structure has a maximum thickness of 5.5-6.5 pm, wherein the constant doping in the silicon mesa is 1.0-3.5×

10¹⁶ cm<sup>−

3</sup>.

17. The device of claim 12, wherein a 750 V device has a specific on-resistance in the range of 0.4-1.0 ohm mm².

18. A method for forming a high-voltage device, comprising:

forming a silicon stripe on a substrate;

forming a silicon mesa in the silicon stripe, wherein the silicon mesa provides a drift region having a constant doping profile;

forming a recessed gate and source on the silicon mesa;

forming a trench adjacent each side of the silicon stripe; and

forming a metal-dielectric field plate structure in each trench along the silicon stripe;

wherein each metal-dielectric field plate structure comprises a dielectric and a metal field plate formed over the dielectric, and wherein a thickness of the dielectric uniformly increases linearly through a portion of a depth of the trench, wherein the dielectric is configured to produce a constant longitudinal electric field through the portion of the depth of the trench.

19. The method of claim 18, further comprising:

forming a dielectric layer or a metal/conductor layer over the metal field plate in the trench, wherein a thickness of the dielectric layer or a thickness of the metal/conductor layer decreases through the depth of the trench.

20. The method of claim 18, wherein the device comprises an n-channel double diffused metal oxide semiconductor transistor or an insulated gate bipolar transistor.