Through silicon via bridge interconnect

• US 7,969,009 B2
• Filed: 06/30/2008
• Issued: 06/28/2011
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chandrasekaran, Arvind
• Primary Examiner(s): Sandvik; Benjamin P
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US12/164,331
• Publication Number:
  US 20090321939A1
• Time in Patent Office: 1,093 Days
• Field of Search: 257/758, 257/E29.002, 257/778
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10272 : Silicon Carbide [SiC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An integrated circuit bridge interconnect system includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The bridge die includes through silicon vias (TSVs) to connect conductive interconnect lines on the bridge die to the first die and the second die. Active circuitry, other than interconnect lines, may be provided on the bridge die. At least one or more additional die may be stacked on the bridge die and interconnected to the bridge die.

Claims

1. An integrated circuit bridge interconnect system, comprising:

a first die having a first side and a second side;

a second die, having a first side and a second side, provided in a side-by-side configuration with the first die; and

a bridge die, having a first side and a second side, disposed at least partially on the first sides of the first die and the second die, the bridge die electrically interconnecting the first die and the second die, the bridge die having bridge die through vias from the first side of the bridge die to the second side of the bridge die, the bridge die through vias being filled with metallizations to connect conductive lines on the first side of the bridge die to enable the interconnecting.

2. The system of claim 1, in which the bridge die further comprises active circuitry on the first side.

3. The system of claim 1, in which one or more contact pads on the second side of the bridge die contact a corresponding one or more contact pads on the first sides of the first and second dies.

4. The system of claim 1, in which at least one of the first and second dies comprise:

a flip-chip die having circuitry disposed on the second side; and

flip-chip through vias from the first side of the flip-chip die to the second side of the flip-chip die, the flip-chip through vias being filled with metallizations to connect active circuitry on the second side of the flip-chip die to one or more contact pads on the first side of the flip-chip die.

5. The system of claim 1, in which at least one of the first and second dies comprises circuitry disposed on the first side of the die.

6. The system of claim 1, further comprising:

one or more contact pads on the first and the second die.

7. The system of claim 6, wherein the bridge die further comprises:

one or more contact pads on the second side of the bridge die corresponding to the bridge die through vias and opposite to and corresponding to the one or more contact pads on the first and/or second die first sides.

8. The system of claim 7, further comprising:

at least one additional die stacked on the bridge die, the at least one additional die further comprising passive, active and/or interconnect circuitry.

9. The system of claim 1, wherein the bridge die is fabricated using a process flow that is different from a process flow corresponding to the first and/or the second dies.

10. An integrated circuit packaging system comprising:

a package to contain semiconductor dies;

a substrate disposed within the package for receiving semiconductor dies;

a first die having a first side and a second side, wherein the first die is disposed on the substrate with the second side facing the substrate;

a second die having a first side and a second side provided in a side-by-side configuration with the first die, wherein the second die is disposed on the substrate with the second side facing the substrate; and

a bridge die, having a first side and a second side, wherein the bridge die is disposed at least partially on the first sides of the first die and the second die, the bridge die interconnecting the first die and the second die, the bridge die comprising bridge die through vias from the first side of the bridge die to the second side of the bridge die, the bridge die through vias being filled with metallization to connect conductive lines on the first side of the bridge die to enable the interconnecting.

11. The packaging system of claim 10, in which the bridge die further comprises active circuitry on the first side.

12. The packaging system of claim 10, in which one or more contact pads on the second side of the bridge die contact a corresponding one or more contact pads on the first sides of the first and second dies.

13. The packaging system of claim 10, in which at least one of the first and second dies comprise:

a flip-chip die having circuitry disposed on the second side, wherein the flip-chip is coupled to the substrate by ball bonding, solder bump bonding or conductive paste;

flip-chip through vias from the first side to the second side of the flip-chip die; and

the flip-chip through vias being filled with metallizations to connect conductive lines on the second side to a one or more contact pads on the first side of the flip-chip die.

14. The packaging system of claim 10, in which at least one of the first and second die comprise circuitry disposed on the first side of the die.

15. The packaging system of claim 10, further comprising:

the first and the second die each having a one or more contact pads.

16. The packaging system of claim 15, wherein the bridge die further comprises:

one or more contact pads on the second side of the bridge die corresponding to the bridge die through vias and opposite to and corresponding to the one or more contact pads on the first and/or second die first sides.

17. The packaging system of claim 16, further comprising:

at least one additional die stacked on the bridge die, the at least one additional die further comprising passive, active and/or interconnect circuitry.

18. The packaging system of claim 10, wherein the bridge die is fabricated using a process flow that is different from a process flow corresponding to the first and/or the second dies.